Trace Interface Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-3
ID012310 Non-Confidential, Unrestricted Access
ETMIABP = ETMIA - <isize>
Table 15-2 lists the ETMIACTL[17:0] instruction interface control signals.
Exception reporting
The ARM1176JZF-S Trace Interface Port is designed for ETMs that support ETMv3.2 or above.
ETMv3.2 permits the determination of each type of exception without reference to the
destination address in the branch packet.
The ETM protocol does not permit the indication of an exception before the first instruction is
traced. If the first instruction traced, when turning on trace, is the instruction at an exception
vector, then the trace does not report an exception. Normally this is not a concern, because you
can expect some missing trace when the trace is turned off.
However, there are two occasions where trace is turned off automatically, so that trace might
lose exceptions even when the ETM is configured to trace continuously:
• the processor enters Debug state
• the processor enters a region where tracing is prohibited, a prohibited region.
Table 15-2 ETMIACTL[17:0]
Bits Reference name Description Qualified by
[17] IASlotKill Kill outstanding slots. IAException
[16] IADAbort Data Abort. IAException
[15] IAExCancel Exception canceled previous instruction. IAException
[12:14] IAExInt b001 = IRQb101 = FIQb100 = Java exception b110 = Precise Data
Abortb000 = Other exception.
IAException
[11] IAException Instruction is an exception vector.
None
a
[10] IABounce Kill the data slot associated with this instruction. There is only ever
one of these instructions. Used for bouncing coprocessor instructions.
IADataInst
[9] IADataInst Instruction is a data instruction. This includes any load, store, or
CPRT, but does not include preloads.
IAInstValid
[8] IAContextID Instruction updates context ID. IAInstValid
[7] IAIndBr Instruction is an indirect branch. IAInstValid
[6] IABpCCFail Branch phantom failed its condition codes. IABpValid
[5] IAInstCCFail Instruction failed its condition codes. IAInstValid
[4] IAJBit Instruction executed in Jazelle state. IAValid
[3] IATBit Instruction executed in Thumb state. IAValid
[2] IABpValid Branch phantom executed this cycle. IAValid
[1] IAInstValid (Non-phantom) instruction executed this cycle. IAValid
[0] IAValid Signals on the instruction interface are valid this cycle. This is kept
LOW when the ETM is powered down.
None
a. The exception signals become valid when the core takes the exception and remain valid until the next instruction is seen at the
exception vector.
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