ARM ARM1176JZF-S User Manual

VFP Exception Handling
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-21
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pessimistic, it is set to the LSA overflow range, to reduce the number of logic terms. Table 22-8
lists the USA and LSA values and conditions. The exponent values in Table 22-8 are in biased
format.
22.12.2 FCMP, FCMPZ, FCMPE, and FCMPEZ
Compare operations do not generate potential exceptions.
Table 22-8 FADD family bounce thresholds
Initial result
exponent
value
Float value
Condition when not in flush-to-zero mode
DP
a
SP
b
SP DP
>
0x7FF - DP overflow - Bounce
0x7FF - DP overflow, NaN, or infinity - Bounce
0x7FE - DP overflow - Bounce
0x7FD - DP overflow - Bounce
0x7FC - DP normal - Normal
>
0x47F > 0xFF SP overflow Bounce Normal
0x47F 0xFF SP NaN or infinity Bounce Normal
0x47E 0xFE SP overflow Bounce Normal
0x47D 0xFD SP overflow Bounce Normal
0x47C 0xFC SP normal Normal Normal
0x3FF 0x7F e = 0 bias value Normal Normal
0x3A0 0x20 SP normal, LSA Minimum, USA Normal
0x39F 0x1F SP underflow, USA Bounce, USA, or normal, LSA Normal
0x381 0x01 SP normal, LSA MIN, LSA Normal
0x380 0x00 SP subnormal Bounce Normal
<
0x380 < 0x00 SP underflow Bounce Normal
0x040 - DP normal, USA - Normal, LSA, or minimum, USA
0x03F - DP underflow, USA - Normal, LSA, or bounce, USA
0x001 - DP normal, LSA - Minimum, LSA, or bounce, USA
0x000 - DP subnormal - Bounce
<
0x000 - DP underflow - Bounce
a. DP = double-precision.
b. SP = single-precision.

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English