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ARM ARM1176JZF-S User Manual
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Introduction
ARM DDI 0301H
Copyright ©
2004-2009 ARM Limited. All rights reser
ved.
1-31
ID012310
Non-Confidential, Unrestricted Access
Figure
1-8 Progression of an LDR that misse
s
See Chapter
16
Cycle T
imings and Interlock Behavior
for details of instruction cycle timings.
MAC3
Not used
Sat
Saturation
Ex3
MAC2
Not used
ALU
Calculate
writeback
value
Ex2
MAC1
Not used
Sh
Shifter
operation
Ex1
1st fetch
stage
Fe1
Fe2
De
Iss
WBex
DC1
DC2
2nd fetch
stage
Instruction
decode
Register
read and
instruction
issue
Base
register
writeback
Data
address
calculation
Writeback
from LSU
ADD
WBls
ALU
pipeline
Load/store
pipeline
Hit under
miss
Common decode pipeline
Multiply
pipeline
First stage
of data
cache
access
Second
stage of
data cache
access
Load
9,10
1234
567
8
56
1
1
1
2
56
58
Table of Contents
Default Chapter
2
Change History
2
Table of Contents
4
Preface
22
About this Book
22
Key to Timing Diagram Conventions
24
Other Publications
25
Feedback
26
Copyright © 2004-2009 ARM Limited. All Rights Reserved
26
Chapter 1 Introduction
28
About the Processor
28
Extensions to Armv6
29
Figure
29
Trustzone Security Extensions
30
ARM1176JZF-S Architecture with Jazelle Technology
32
Components of the Processor
34
Figure 1-1 ARM1176JZF-S Processor Block Diagram
34
Figure
39
Table 1-1 TCM Configurations
39
Figure
40
Coprocessor Interface
43
Conditional Execution
35
Figure
37
Table 1-2 Double-Precision VFP Operations
46
Table 1-3 Flush-To-Zero Mode
46
Power Management
49
Configurable Options
51
Table 1-4 Configurable Options
51
Table 1-5 ARM1176JZF-S Processor Default Configurations
51
Pipeline Stages
52
Figure 1-2 ARM1176JZF-S Pipeline Stages
52
Typical Pipeline Operations
54
Figure 1-3 Typical Operations in Pipeline Stages
54
Figure 1-4 Typical ALU Operation
54
Figure 1-5 Typical Multiply Operation
55
Figure 1-6 Progression of an LDR/STR Operation
56
Figure 1-7 Progression of an LDM/STM Operation
56
Figure 1-8 Progression of an LDR that Misses
57
ARM1176JZF-S Instruction Set Summary
58
Table 1-7 ARM Instruction Set Summary
59
Table
64
Table 1-8 Addressing Mode 2
67
Table 1-9 Addressing Mode 2P, Post-Indexed Only
67
Addressing Mode 3
68
Addressing Mode 4
68
Addressing Mode 5
68
Table 1-13 Operand2
69
Table 1-14 Fields
69
Table 1-15 Condition Codes
69
Table 1-16 Thumb Instruction Set Summary
70
Product Revisions
73
Chapter 2 Programmer's Model
75
About the Programmer's Model
75
Secure World and Non-Secure World Operation with Trustzone
76
Figure 2-1 Secure and Non-Secure Worlds
76
Figure 2-2 Memory in the Secure and Non-Secure Worlds
79
Figure 2-3 Memory Partition in the Secure and Non-Secure Worlds
80
Figure
81
Table 2-1 Write Access Behavior for System Control Processor Registers
82
Table 2-2 Secure Monitor Bus Signals
84
Processor Operating States
85
Instruction Length
86
Data Types
87
Memory Formats
88
Figure 2-4 Big-Endian Addresses of Bytes Within Words
88
Figure 2-5 Little-Endian Addresses of Bytes Within Words
88
Addresses in a Processor System
89
Table 2-3 Address Types in the Processor System
89
Operating Modes
90
Table 2-4 Mode Structure
90
Registers
91
Figure
91
Table 2-5 Register Mode Identifiers
92
Figure
92
Figure 2-6 Register Organization in ARM State
93
Figure 2-7 Processor Core Register Set Showing Banked Registers
94
Figure 2-8 Register Organization in Thumb State
95
Figure 2-9 ARM State and Thumb State Registers Relationship
96
The Program Status Registers
97
Figure 2-10 Program Status Register
97
Table 2-6 GE[3:0] Settings
99
Table 2-7 PSR Mode Bit Values
101
Additional Instructions
103
Copyright © 2004-2009 ARM Limited. All Rights Reserved
103
Figure 2-11 LDREXB Instruction
103
Figure 2-12 STREXB Instructions
103
Figure 2-13 LDREXH Instruction
104
Figure 2-14 STREXH Instruction
105
Figure 2-15 LDREXD Instruction
106
Figure 2-16 STREXD Instruction
106
Figure 2-17 CLREX Instruction
107
Figure 2-18 NOP-Compatible Hint Instruction
107
Exceptions
109
Table 2-8 Exception Entry and Exit
110
Exception Vectors
121
Table 2-9 Exception Priorities
130
Figure
130
Software Considerations
132
Chapter 3 System Control Coprocessor
133
About the System Control Coprocessor
134
Table 3-1 System Control Coprocessor Register Functions
135
Figure 3-1 System Control and Configuration Registers
137
Figure 3-2 MMU Control and Configuration Registers
139
Figure 3-3 Cache Control and Configuration Registers
140
Figure 3-4 TCM Control and Configuration Registers
140
Figure 3-5 Cache Master Valid Registers
141
Figure 3-6 DMA Control and Configuration Registers
141
Figure 3-7 System Performance Monitor Registers
142
Figure 3-8 System Validation Registers
143
Figure 3-9 CP15 MRC and MCR Bit Pattern
144
System Control Processor Registers
145
Table 3-2 Summary of CP15 Registers and Operations
146
Table 3-3 Summary of CP15 MCRR Operations
151
Figure 3-10 Main ID Register Format
152
Table 3-4 Main ID Register Bit Functions
152
Table 3-5 Results of Access to the Main ID Register
152
Figure 3-11 Cache Type Register Format
153
Table 3-6 Cache Type Register Bit Functions
153
Table 3-7 Results of Access to the Cache Type Register
155
Table 3-8 Example Cache Type Register Format
155
Figure 3-12 TCM Status Register Format
156
Table 3-9 TCM Status Register Bit Functions
156
Figure 3-13 TLB Type Register Format
157
Table 3-10 TLB Type Register Bit Functions
157
Table 3-11 Results of Access to the TLB Type Register
157
Figure 3-14 Processor Feature Register 0 Format
158
Table 3-12 Processor Feature Register 0 Bit Functions
158
Table 3-13 Results of Access to the Processor Feature Register 0
159
Figure 3-15 Processor Feature Register 1 Format
160
Table 3-14 Processor Feature Register 1 Bit Functions
160
Table 3-15 Results of Access to the Processor Feature Register 1
160
Figure 3-16 Debug Feature Register 0 Format
161
Table 3-16 Debug Feature Register 0 Bit Functions
161
Table 3-17 Results of Access to the Debug Feature Register 0
161
Table 3-18 Auxiliary Feature Register 0 Bit Functions
162
Table 3-19 Results of Access to the Auxiliary Feature Register 0
162
Figure 3-17 Memory Model Feature Register 0 Format
163
Table 3-20 Memory Model Feature Register 0 Bit Functions
163
Table 3-21 Results of Access to the Memory Model Feature Register 0
163
Figure 3-18 Memory Model Feature Register 1 Format
164
Table 3-22 Memory Model Feature Register 1 Bit Functions
164
Table 3-23 Results of Access to the Memory Model Feature Register 1
165
Figure 3-19 Memory Model Feature Register 2 Format
166
Table 3-24 Memory Model Feature Register 2 Bit Functions
166
Figure 3-20 Memory Model Feature Register 3 Format
167
Table 3-25 Results of Access to the Memory Model Feature Register 2
167
Table 3-26 Memory Model Feature Register 3 Bit Functions
167
Figure 3-21 Instruction Set Attributes Register 0 Format
168
Table 3-27 Results of Access to the Memory Model Feature Register 3
168
Table 3-28 Instruction Set Attributes Register 0 Bit Functions
168
Table 3-29 Results of Access to the Instruction Set Attributes Register 0
169
Figure 3-22 Instruction Set Attributes Register 1 Format
170
Table 3-30 Instruction Set Attributes Register 1 Bit Functions
170
Table 3-31 Results of Access to the Instruction Set Attributes Register 1
170
Figure 3-23 Instruction Set Attributes Register 2 Format
171
Table 3-32 Instruction Set Attributes Register 2 Bit Functions
171
Figure 3-24 Instruction Set Attributes Register 3 Format
172
Table 3-33 Results of Access to the Instruction Set Attributes Register 2
172
Table 3-34 Instruction Set Attributes Register 3 Bit Functions
173
Table 3-35 Results of Access to the Instruction Set Attributes Register 3
173
Figure 3-25 Instruction Set Attributes Register 4 Format
174
Table 3-36 Instruction Set Attributes Register 4 Bit Functions
174
Table 3-37 Results of Access to the Instruction Set Attributes Register 4
175
Table 3-38 Results of Access to the Instruction Set Attributes Register 5
175
Figure 3-26 Control Register Format
176
Figure
177
Table 3-39 Control Register Bit Functions
177
Figure
179
Table 3-40 Results of Access to the Control Register
179
Table 3-41 Resultant B Bit, U Bit, and EE Bit Values
180
Figure 3-27 Auxiliary Control Register Format
181
Table 3-42 Auxiliary Control Register Bit Functions
181
Table 3-43 Results of Access to the Auxiliary Control Register
182
Figure 3-28 Coprocessor Access Control Register Format
183
Table 3-44 Coprocessor Access Control Register Bit Functions
183
Table 3-45 Results of Access to the Coprocessor Access Control Register
183
Figure 3-29 Secure Configuration Register Format
184
Table 3-46 Secure Configuration Register Bit Functions
184
Table 3-47 Operation of the FW and FIQ Bits
185
Table 3-48 Operation of the AW and EA Bits
185
Figure 3-30 Secure Debug Enable Register Format
186
Table 3-49 Secure Debug Enable Register Bit Functions
186
Table 3-50 Results of Access to the Coprocessor Access Control Register
187
Figure 3-31 Non-Secure Access Control Register Format
188
Table 3-51 Non-Secure Access Control Register Bit Functions
188
Figure 3-32 Translation Table Base Register 0 Format
189
Table 3-52 Results of Access to the Auxiliary Control Register
189
Table 3-53 Translation Table Base Register 0 Bit Functions
190
Table 3-54 Results of Access to the Translation Table Base Register 0
190
Figure 3-33 Translation Table Base Register 1 Format
191
Table 3-55 Translation Table Base Register 1 Bit Functions
191
Table 3-56 Results of Access to the Translation Table Base Register 1
192
Figure 3-34 Translation Table Base Control Register Format
193
Table 3-57 Translation Table Base Control Register Bit Functions
193
Table 3-58 Results of Access to the Translation Table Base Control Register
194
Figure 3-35 Domain Access Control Register Format
195
Table 3-59 Domain Access Control Register Bit Functions
195
Table 3-60 Results of Access to the Domain Access Control Register
195
Figure 3-36 Data Fault Status Register Format
196
Table 3-61 Data Fault Status Register Bit Functions
196
Figure 3-37 Instruction Fault Status Register Format
198
Table 3-62 Results of Access to the Data Fault Status Register
198
Table 3-63 Instruction Fault Status Register Bit Functions
199
Table 3-64 Results of Access to the Instruction Fault Status Register
199
Table 3-65 Results of Access to the Fault Address Register
200
Table 3-66 Results of Access to the Instruction Fault Address Register
201
Figure 3-38 Cache Operations
202
Figure 3-39 Cache Operations with MCRR Instructions
203
Figure 3-40 C7 Format for Set and Index
204
Table 3-67 Functional Bits of C7 for Set and Index
204
Table 3-68 Cache Size and S Parameter Dependency
204
Figure 3-41 C7 Format for MVA
205
Figure 3-42 Format of C7 for VA
205
Table 3-69 Functional Bits of C7 for MVA
205
Table 3-70 Functional Bits of C7 for VA Format
206
Table 3-71 Cache Operations for Entire Cache
206
Table 3-72 Cache Operations for Single Lines
207
Table 3-73 Cache Operations for Address Ranges
208
Figure
209
Figure 3-43 Cache Dirty Status Register Format
210
Table 3-74 Cache Dirty Status Register Bit Functions
210
Figure 3-44 C7 Format for Flush Branch Target Entry Using MVA
211
Table 3-75 Cache Operations Flush Functions
211
Table 3-76 Flush Branch Target Entry Using MVA Bit Functions
211
Figure 3-45 PA Register Format for Successful Translation
212
Figure 3-46 PA Register Format for Aborted Translation
212
Table 3-77 PA Register for Successful Translation Bit Functions
212
Table 3-78 PA Register for Unsuccessful Translation Bit Functions
213
Table 3-79 Results of Access to the Data Synchronization Barrier Operation
216
Table 3-80 Results of Access to the Data Memory Barrier Operation
217
Table 3-81 Results of Access to the Wait for Interrupt Operation
217
Table 3-82 Results of Access to the TLB Operations Register
218
Figure 3-47 TLB Operations Register MVA and ASID Format
219
Figure 3-48 TLB Operations Register ASID Format
219
Figure 3-49 Instruction and Data Cache Lockdown Register Formats
220
Table 3-83 Instruction and Data Cache Lockdown Register Bit Functions
220
Table 3-84 Results of Access to the Instruction and Data Cache Lockdown Register
220
Figure 3-50 Data TCM Region Register Format
222
Table 3-85 Data TCM Region Register Bit Functions
222
Figure 3-51 Instruction TCM Region Register Format
223
Table 3-86 Results of Access to the Data TCM Region Register
223
Table 3-87 Instruction TCM Region Register Bit Functions
224
Figure 3-52 Data TCM Non-Secure Control Access Register Format
225
Table 3-88 Results of Access to the Instruction TCM Region Register
225
Table 3-89 Data TCM Non-Secure Control Access Register Bit Functions
226
Table 3-90 Effects of NS Items for Data TCM Operation
226
Figure 3-53 Instruction TCM Non-Secure Control Access Register Format
227
Table 3-91 Instruction TCM Non-Secure Control Access Register Bit Functions
227
Table 3-92 Effects of NS Items for Instruction TCM Operation
227
Figure 3-54 TCM Selection Register Format
228
Table 3-93 TCM Selection Register Bit Functions
228
Figure 3-55 Cache Behavior Override Register Format
229
Table 3-94 Results of Access to the TCM Selection Register
229
Table 3-95 Cache Behavior Override Register Bit Functions
230
Table 3-96 Results of Access to the Cache Behavior Override Register
230
Figure 3-56 TLB Lockdown Register Format
232
Table 3-97 TLB Lockdown Register Bit Functions
232
Table 3-98 Results of Access to the TLB Lockdown Register
232
Figure 3-57 Primary Region Remap Register Format
234
Table 3-99 Primary Region Remap Register Bit Functions
234
Figure 3-58 Normal Memory Remap Register Format
235
Table 3-100 Encoding for the Remapping of the Primary Memory Type
235
Table 3-101 Normal Memory Remap Register Bit Functions
235
Table 3-102 Remap Encoding for Inner or Outer Cacheable Attributes
236
Table 3-103 Results of Access to the Memory Region Remap Registers
236
Figure 3-59 DMA Identification and Status Registers Format
238
Table 3-104 DMA Identification and Status Register Bit Functions
238
Table 3-105 DMA Identification and Status Register Functions
238
Table 3-106 Results of Access to the DMA Identification and Status Registers
239
Figure 3-60 DMA User Accessibility Register Format
240
Table 3-107 DMA User Accessibility Register Bit Functions
240
Table 3-108 Results of Access to the DMA User Accessibility Register
240
Figure 3-61 DMA Channel Number Register Format
241
Table 3-109 DMA Channel Number Register Bit Functions
241
Table 3-110 Results of Access to the DMA Channel Number Register
241
Table 3-111 Results of Access to the DMA Enable Registers
243
Figure 3-62 DMA Control Register Format
244
Table 3-112 DMA Control Register Bit Functions
244
Table 3-113 Results of Access to the DMA Control Register
245
Table 3-114 Results of Access to the DMA Internal Start Address Register
246
Table 3-115 Results of Access to the DMA External Start Address Register
247
Table 3-116 Results of Access to the DMA Internal End Address Register
248
Figure 3-63 DMA Channel Status Register Format
249
Table 3-117 DMA Channel Status Register Bit Functions
249
Table 3-118 Results of Access to the DMA Channel Status Register
251
Figure 3-64 DMA Context ID Register Format
252
Table 3-119 DMA Context ID Register Bit Functions
252
Table 3-120 Results of Access to the DMA Context ID Register
252
Figure 3-65 Secure or Non-Secure Vector Base Address Register Format
253
Table 3-121 Secure or Non-Secure Vector Base Address Register Bit Functions
253
Figure 3-66 Monitor Vector Base Address Register Format
254
Table 3-122 Results of Access to the Secure or Non-Secure Vector Base Address Register
254
Table 3-123 Monitor Vector Base Address Register Bit Functions
255
Table 3-124 Results of Access to the Monitor Vector Base Address Register
255
Figure 3-67 Interrupt Status Register Format
256
Table 3-125 Interrupt Status Register Bit Functions
256
Table 3-126 Results of Access to the Interrupt Status Register
256
Figure 3-68 FCSE PID Register Format
258
Table 3-127 FCSE PID Register Bit Functions
258
Table 3-128 Results of Access to the FCSE PID Register
258
Figure 3-69 Address Mapping with the FCSE PID Register
259
Figure 3-70 Context ID Register Format
260
Table 3-129 Context ID Register Bit Functions
260
Table 3-130 Results of Access to the Context ID Register
260
Table 3-131 Results of Access to the Thread and Process ID Registers
261
Figure 3-71 Peripheral Port Memory Remap Register Format
262
Table 3-132 Peripheral Port Memory Remap Register Bit Functions
263
Table 3-133 Results of Access to the Peripheral Port Remap Register
263
Figure 3-72 Secure User and Non-Secure Access Validation Control Register Format
264
Table 3-134 Secure User and Non-Secure Access Validation Control Register Bit Functions
264
Figure 3-73 Performance Monitor Control Register Format
265
Table 3-136 Performance Monitor Control Register Bit Functions
266
Table 3-137 Performance Monitoring Events
267
Table 3-138 Results of Access to the Performance Monitor Control Register
269
Table 3-139 Results of Access to the Cycle Counter Register
270
Table 3-140 Results of Access to the Count Register 0
271
Table 3-141 Results of Access to the Count Register 1
272
Table 3-142 System Validation Counter Register Operations
272
Table 3-143 Results of Access to the System Validation Counter Register
273
Figure 3-74 System Validation Counter Register Format for External Debug Request Counter
273
Table 3-144 System Validation Operations Register Functions
274
Table 3-145 Results of Access to the System Validation Operations Register
275
Table 3-146 System Validation Cache Size Mask Register Bit Functions
277
Figure 3-75 System Validation Cache Size Mask Register Format
277
Table 3-147 Results of Access to the System Validation Cache Size Mask Register
278
Table 3-148 TLB Lockdown Index Register Bit Functions
281
Figure 3-76 TLB Lockdown Index Register Format
281
Figure 3-77 TLB Lockdown VA Register Format
281
Table 3-149 TLB Lockdown VA Register Bit Functions
282
Table 3-150 TLB Lockdown PA Register Bit Functions
282
Figure 3-78 TLB Lockdown PA Register Format
282
Table 3-151 Access Permissions APX and AP Bit Fields Encoding
283
Table 3-152 TLB Lockdown Attributes Register Bit Functions
283
Figure 3-79 TLB Lockdown Attributes Register Format
283
Table 3-153 Results of Access to the TLB Lockdown Access Registers
284
Chapter 4 Unaligned and Mixed-Endian Data Access Support
287
About Unaligned and Mixed-Endian Support
287
Unaligned Access Support
288
Table 4-1 Unaligned Access Handling
289
Endian Support
291
Figure 4-1 Load Unsigned Byte
291
Figure 4-2 Load Signed Byte
291
Figure 4-3 Store Byte
292
Figure 4-4 Load Unsigned Halfword, Little-Endian
292
Figure 4-5 Load Unsigned Halfword, Big-Endian
293
Figure 4-6 Load Signed Halfword, Little-Endian
293
Figure 4-7 Load Signed Halfword, Big-Endian
294
Figure 4-8 Store Halfword, Little-Endian
294
Figure 4-9 Store Halfword, Big-Endian
295
Figure 4-10 Load Word, Little-Endian
295
Figure 4-11 Load Word, Big-Endian
296
Figure 4-12 Store Word, Little-Endian
296
Figure 4-13 Store Word, Big-Endian
297
Operation of Unaligned Accesses
298
Table 4-2 Memory Access Types
298
Table 4-3 Unalignment Fault Occurrence When Access Behavior Is Architecturally Unpredictable
299
Mixed-Endian Access Support
302
Table 4-4 Legacy Endianness Using CP15 C1
302
Figure
302
Table 4-5 Mixed-Endian Configuration
304
Table 4-6 B Bit, U Bit, and EE Bit Settings
304
Instructions to Reverse Bytes in a General-Purpose Register
305
Instructions to Change the CPSR E Bit
306
Chapter 5 Program Flow Prediction
307
About Program Flow Prediction
308
Branch Prediction
310
Return Stack
313
Memory Barriers
314
ARM1176JZF-S IMB Implementation
316
Chapter 6 Memory Management Unit
319
About the MMU
319
TLB Organization
321
Figure
321
Figure
323
Memory Access Sequence
324
Enabling and Disabling the MMU
326
Memory Access Control
328
Table 6-1 Access Permission Bit Encoding
329
Figure
330
Memory Region Attributes
331
Figure
331
Table 6-2 TEX Field, and C and B Bit Encodings Used in Page Table Formats
332
Table 6-3 Cache Policy Bits
333
Table 6-4 Inner and Outer Cache Policy Implementation Options
333
Table 6-5 Effect of Remapping Memory with TEX Remap = 1
334
Table 6-6 Values that Remap the Shareable Attribute
335
Table 6-7 Primary Region Type Encoding
335
Table 6-8 Inner and Outer Region Remap Encoding
335
Figure
336
Memory Attributes and Types
337
Table 6-9 Memory Attributes
337
Figure
340
Figure 6-1 Memory Ordering Restrictions
341
Table 6-10 Memory Region Backwards Compatibility
343
MMU Aborts
344
MMU Fault Checking
346
Translation Table Managed TLB Fault Checking Sequence Part 1
347
Figure
347
Translation Table Managed TLB Fault Checking Sequence Part 2
348
Fault Status and Address
351
Table 6-11 Fault Status Register Encoding
351
Table 6-12 Summary of Aborts
352
Hardware Page Table Translation
353
Figure 6-4 Backwards-Compatible First-Level Descriptor Format
354
Figure 6-5 Backwards-Compatible Second-Level Descriptor Format
355
Figure 6-6 Backwards-Compatible Section, Supersection, and Page Translation
355
Figure 6-7 Armv6 First-Level Descriptor Formats with Subpages Disabled
356
Figure 6-8 Armv6 Second-Level Descriptor Format
357
Figure 6-9 Armv6 Section, Supersection, and Page Translation
358
MMU Descriptors
360
Table 6-13 Translation Table Size
360
Figure 6-10 Creating a First-Level Descriptor Address
361
Table 6-14 Access Types from First-Level Descriptor Bit Values
362
Translation for a 1MB Section, Armv6 Format
363
Translation for a 1MB Section, Backwards-Compatible Format
363
Table 6-15 Access Types from Second-Level Descriptor Bit Values
364
Generating a Second-Level Page Table Address
364
Figure 6-14 Large Page Table Walk, Armv6 Format
365
Figure 6-15 Large Page Table Walk, Backwards-Compatible Format
366
Figure 6-16 4KB Small Page or 1KB Small Subpage Translations, Backwards-Compatible Format
367
Figure 6-17 4KB Extended Small Page Translations, Armv6 Format
368
Figure 6-18 4KB Extended Small Page or 1KB Extended Small Subpage Translations
369
MMU Software-Accessible Registers
370
Table 6-16 CP15 Register Functions
370
Table 6-17 CP14 Register Functions
371
Chapter 7 Level One Memory System
373
About the Level One Memory System
373
Figure
373
Cache Organization
374
Figure
374
Figure 7-1 Level One Cache Block Diagram
375
Tightly-Coupled Memory
378
Table 7-1 TCM Configurations
378
Table 7-2 Access to Non-Secure TCM
379
Table 7-3 Access to Secure TCM
379
Dma
381
TCM and Cache Interactions
383
Table 7-4 Summary of Data Accesses to TCM and Caches
385
Table 7-5 Summary of Instruction Accesses to TCM and Caches
386
Write Buffer
387
Chapter 8 Level Two Interface
389
About the Level Two Interface
389
Figure 8-1 Level Two Interconnect Interfaces
389
Table 8-1 AXI Parameters for the Level 2 Interconnect Interfaces
390
Dma Interface
392
Synchronization Primitives
393
AXI Control Signals in the Processor
395
Figure 8-2 Channel Architecture of Reads
395
Figure 8-3 Channel Architecture of Writes
395
Table 8-2 Axlen[3:0] Encoding
397
Table 8-3 Axsize[2:0] Encoding
398
Table 8-4 Axburst[1:0] Encoding
398
Table 8-5 Axlock[1:0] Encoding
398
Table 8-6 Axcache[3:0] Encoding
399
Table 8-7 Axprot[2:0] Encoding
399
Table 8-8 Axsideband[4:1] Encoding
400
Table 8-9 ARSIDEBANDI[4:1] Encoding
400
Instruction Fetch Interface Transfers
401
Table 8-10 AXI Signals for Cacheable Fetches
401
Table 8-11 AXI Signals for Noncacheable Fetches
401
Data Read/Write Interface Transfers
402
Table 8-12 Linefill Behavior on the AXI Interface
402
Table 8-13 Noncacheable LDRB
403
Table 8-14 Noncacheable LDRH
403
Table 8-15 Noncacheable LDR or LDM1
404
Table 8-16 Noncacheable LDRD or LDM2
404
Noncacheable LDRD or LDM2 from Word 7
405
Table 8-18 Noncacheable LDM3, Strongly Ordered or Device Memory
405
Table 8-19 Noncacheable LDM3, Noncacheable Memory or Cache Disabled
405
Noncacheable LDM3 from Word 6, or 7
405
Table 8-21 Noncacheable LDM4, Strongly Ordered or Device Memory
406
Table 8-22 Noncacheable LDM4, Noncacheable Memory or Cache Disabled
406
Noncacheable LDM4 from Word 5, 6, or 7
406
Table 8-24 Noncacheable LDM5, Strongly Ordered or Device Memory
407
Table 8-25 Noncacheable LDM5, Noncacheable Memory or Cache Disabled
407
Table 8-27 Noncacheable LDM6, Strongly Ordered or Device Memory
407
Noncacheable LDM5 from Word 4, 5, 6, or 7
407
Table 8-28 Noncacheable LDM6, Noncacheable Memory or Cache Disabled
408
Noncacheable LDM6 from Word 3, 4, 5, 6, or 7
408
Table 8-30 Noncacheable LDM7, Strongly Ordered or Device Memory
408
Table 8-31 Noncacheable LDM7, Noncacheable Memory or Cache Disabled
408
Table 8-32 Noncacheable LDM7 from Word 2, 3, 4, 5, 6, or 7
409
Noncacheable LDM8 from Word 1, 2, 3, 4, 5, 6, or 7
409
Table 8-35 Noncacheable LDM9
409
Table 8-36 Noncacheable LDM10
410
Table 8-37 Noncacheable LDM11
410
Table 8-38 Noncacheable LDM12
411
Table 8-39 Noncacheable LDM13
411
Table 8-40 Noncacheable LDM14
411
Table 8-41 Noncacheable LDM15
412
Table 8-42 Noncacheable LDM16
412
Table 8-43 Half-Line Write-Back
413
Table 8-44 Full-Line Write-Back
413
Table 8-45 Cacheable Write-Through or Noncacheable STRB
414
Table 8-46 Cacheable Write-Through or Noncacheable STRH
414
Table 8-47 Cacheable Write-Through or Noncacheable STR or STM1
415
Cacheable Write-Through or Noncacheable STRD or STM2 to Words 0, 1, 2, 3, 4, 5, or 6
416
Cacheable Write-Through or Noncacheable STM2 to Word 7
416
Cacheable Write-Through or Noncacheable STM3 to Words 0, 1, 2, 3, 4, or 5
416
Cacheable Write-Through or Noncacheable STM3 to Words 6 or 7
416
Cacheable Write-Through or Noncacheable STM4 to Word 0, 1, 2, 3, or 4
417
Cacheable Write-Through or Noncacheable STM4 to Word 5, 6, or 7
417
Cacheable Write-Through or Noncacheable STM5 to Word 0, 1, 2, or 3
417
Cacheable Write-Through or Noncacheable STM5 to Word 4, 5, 6, or 7
417
Cacheable Write-Through or Noncacheable STM6 to Word 0, 1, or 2
418
Cacheable Write-Through or Noncacheable STM6 to Word 3, 4, 5, 6, or 7
418
Cacheable Write-Through or Noncacheable STM7 to Word 0 or 1
418
Cacheable Write-Through or Noncacheable STM7 to Word 2, 3, 4, 5, 6 or 7
419
Cacheable Write-Through or Noncacheable STM8 to Word 0
419
Cacheable Write-Through or Noncacheable STM8 to Word 1, 2, 3, 4, 5, 6, or 7
419
Table 8-62 Cacheable Write-Through or Noncacheable STM9
419
Table 8-63 Cacheable Write-Through or Noncacheable STM10
420
Table 8-64 Cacheable Write-Through or Noncacheable STM11
420
Table 8-65 Cacheable Write-Through or Noncacheable STM12
421
Table 8-66 Cacheable Write-Through or Noncacheable STM13
421
Table 8-67 Cacheable Write-Through or Noncacheable STM14
422
Table 8-68 Cacheable Write-Through or Noncacheable STM15
422
Table 8-69 Cacheable Write-Through or Noncacheable STM16
423
Peripheral Interface Transfers
424
Table 8-70 Example Peripheral Interface Reads and Writes
424
Endianness
425
Figure 8-4 Swizzling of Data and Strobes in BE-32 Big-Endian Configuration
425
Locked Access
426
Chapter 9 Clocking and Resets
428
About Clocking and Resets
428
Clocking and Resets with no IEM
429
Figure 9-1 Processor Clocks with no IEM
429
Figure 9-2 Read Latency with no IEM
430
Clocking and Resets with IEM
431
Figure
431
Figure 9-3 Processor Clocks with IEM
432
Figure 9-4 Processor Synchronization with IEM
432
Figure 9-5 Read Latency with IEM
434
Reset Modes
436
Table 9-1 Reset Modes
436
Figure 9-6 Power-On Reset
436
Chapter 10 Power Control
438
About Power Control
439
Power Management
440
VFP Shutdown
443
Intelligent Energy Management
444
Figure
444
Chapter 11 Coprocessor Interface
445
Figure 10-1 IEM Structure
445
About the Coprocessor Interface
447
Coprocessor Pipeline
448
Table 11-1 Coprocessor Instructions
448
Table 11-2 Coprocessor Control Signals
449
Figure
449
Figure 11-1 Core and Coprocessor Pipelines
450
Figure 11-2 Coprocessor Pipeline and Queues
450
Figure 11-3 Coprocessor Pipeline
451
Table 11-3 Pipeline Stage Update
452
Token Queue Management
454
Figure 11-4 Token Queue Buffers
454
Table 11-4 Addressing of Queue Buffers
455
Figure 11-5 Queue Reading and Writing
455
Figure 11-6 Queue Flushing
456
Token Queues
457
Figure 11-7 Instruction Queue
457
Data Transfer
460
Figure 11-8 Coprocessor Data Transfer
460
Figure 11-9 Instruction Iteration for Loads
461
Figure 11-10 Load Data Buffering
462
Operations
464
Table 11-5 Retirement Conditions
465
Multiple Coprocessors
467
Chapter 12 Vectored Interrupt Controller Port
469
About the PL192 Vectored Interrupt Controller
469
About the Processor VIC Port
470
Table 12-1 VIC Port Signals
470
Figure 12-1 Connection of a VIC to the Processor
470
Timing of the VIC Port
472
Figure 12-2 VIC Port Timing Example
472
Interrupt Entry Flowchart
474
Figure 12-3 Interrupt Entry Sequence
474
Chapter 13 Debug
476
Debug Systems
476
Figure 13-1 Typical Debug System
476
About the Debug Unit
477
Debug Registers
479
Table 13-1 Terms Used in Register Descriptions
479
Table 13-2 CP14 Debug Register Map
479
Figure 13-2 Debug ID Register Format
480
Table 13-3 Debug ID Register Bit Field Definition
481
Figure
481
Table 13-4 Debug Status and Control Register Bit Field Definitions
482
Figure 13-3 Debug Status and Control Register Format
482
Table 13-5 Data Transfer Register Bit Field Definitions
486
Figure 13-4 DTR Format
486
Figure 13-5 Vector Catch Register Format
487
Table 13-6 Vector Catch Register Bit Field Definitions
488
Table 13-7 Summary of Debug Entry and Exception Conditions
488
Table 13-8 Processor Breakpoint and Watchpoint Registers
490
Table 13-9 Breakpoint Value Registers, Bit Field Definition
491
Table 13-10 Processor Breakpoint Control Registers
491
Figure 13-6 Breakpoint Control Registers, Format
491
Table 13-11 Breakpoint Control Registers, Bit Field Definitions
492
Table 13-12 Meaning of BCR[22:20] Bits
493
Table 13-13 Processor Watchpoint Value Registers
494
Table 13-14 Watchpoint Value Registers, Bit Field Definitions
495
Table 13-15 Processor Watchpoint Control Registers
495
Table 13-16 Watchpoint Control Registers, Bit Field Definitions
495
Figure 13-7 Watchpoint Control Registers, Format
495
Table 13-17 Debug State Cache Control Register Bit Functions
497
Table 13-18 Debug State MMU Control Register Bit Functions
498
CP14 Registers Reset
499
CP14 Debug Instructions
500
Table 13-19 CP14 Debug Instructions
500
Table 13-20 Debug Instruction Execution
501
External Debug Interface
502
Table 13-21 Secure Debug Behavior
502
Changing the Debug Enable Signals
505
Debug Events
506
Table 13-22 Behavior of the Processor on Debug Events
507
Table 13-23 Setting of CP15 Registers on Debug Events
508
Debug Exception
509
Table 13-24 Values in the Link Register after Exceptions
510
13.10 Debug State
511
Table 13-25 Read PC Value after Debug State Entry
513
Table 13-26 Example Memory Operation Sequence
515
13.11 Debug Communications Channel
516
13.12 Debugging in a Cached System
517
13.13 Debugging in a System with Tlbs
518
13.14 Monitor Debug-Mode Debugging
519
13.15 Halting Debug-Mode Debugging
524
13.16 External Signals
526
Chapter 14 Debug Test Access Port
528
Debug Test Access Port and Debug State
528
Figure 14-1 JTAG DBGTAP State Machine Diagram
528
Synchronizing Realview ICE
529
Figure 14-2 Realview ICE Clock Synchronization
529
Entering Debug State
530
Exiting Debug State
531
The DBGTAP Port and Debug Registers
532
Table 14-1 Supported Public Instructions
532
Debug Registers
534
Figure 14-3 Bypass Register Bit Order
534
Figure 14-4 Device ID Code Register Bit Order
535
Figure 14-5 Instruction Register Bit Order
535
Figure 14-6 Scan Chain Select Register Bit Order
536
Figure 14-7 Scan Chain 0 Bit Order
537
Figure 14-8 Scan Chain 1 Bit Order
537
Figure 14-9 Scan Chain 4 Bit Order
539
Figure 14-10 Scan Chain 5 Bit Order, EXTEST Selected
541
Figure 14-11 Scan Chain 5 Bit Order, INTEST Selected
541
Figure 14-12 Scan Chain 6 Bit Order
543
Figure 14-13 Scan Chain 7 Bit Order
544
Table 14-2 Scan Chain 7 Register Map
545
Using the Debug Test Access Port
547
Figure 14-14 Behavior of the Itrsel IR Instruction
548
Debug Sequences
555
Programming Debug Events
566
14.10 Monitor Debug-Mode Debugging
568
Chapter 15 Trace Interface Port
569
About the ETM Interface
570
Table 15-1 Instruction Interface Signals
570
Table 15-2 ETMIACTL[17:0]
571
Table 15-3 ETMIASECCTL[1:0]
572
Table 15-4 Data Address Interface Signals
572
Table 15-5 ETMDACTL[17:0]
573
Table 15-6 Data Value Interface Signals
574
Table 15-7 ETMDDCTL[3:0]
574
Table 15-8 ETMPADV[2:0]
574
Table 15-9 Coprocessor Interface Signals
575
Table 15-10 ETMCPSECCTL[1:0] Format
575
Figure 15-1 ETMCPADDRESS Format
575
Table 15-11 Other Connections
576
Figure
576
Chapter 16 Cycle Timings and Interlock Behavior
577
About Cycle Timings and Interlock Behavior
578
Table 16-1 Pipeline Stages
579
Conditional Instructions
580
Table 16-2 Definition of Cycle Timing Terms
581
Register Interlock Examples
582
Table 16-3 Register Interlock Examples
582
Data Processing Instructions
583
Table 16-4 Data Processing Instruction Cycle Timing Behavior if Destination Is Not PC
583
Table 16-5 Data Processing Instruction Cycle Timing Behavior if Destination Is the PC
583
QADD, QDADD, QSUB, and QDSUB Instructions
585
Table 16-6 QADD, QDADD, QSUB, and QDSUB Instruction Cycle Timing Behavior
585
Armv6 Media Data-Processing
586
Table 16-7 Armv6 Media Data-Processing Instructions Cycle Timing Behavior
586
Armv6 Sum of Absolute Differences (SAD)
587
Table 16-8 Armv6 Sum of Absolute Differences Instruction Timing Behavior
587
Table 16-9 Example Interlocks
587
Multiplies
588
Table 16-10 Example Multiply Instruction Cycle Timing Behavior
588
Branches
590
Table 16-11 Branch Instruction Cycle Timing Behavior
590
Processor State Updating Instructions
591
Table 16-12 Processor State Updating Instructions Cycle Timing Behavior
591
16.10 Single Load and Store Instructions
592
Table 16-13 Cycle Timing Behavior for Stores and Loads, Other than Loads to the PC
592
Table 16-14 Cycle Timing Behavior for Loads to the PC
593
Table 16-15 <Addr_Md_1Cycle> and <Addr_Md_2Cycle> LDR Example Instruction Explanation
593
16.11 Load and Store Double Instructions
595
Table 16-16 Load and Store Double Instructions Cycle Timing Behavior
595
Table 16-17 <Addr_Md_1Cycle> and <Addr_Md_2Cycle> LDRD Example Instruction Explanation
595
16.12 Load and Store Multiple Instructions
597
Table 16-18 Cycle Timing Behavior of Load and Store Multiples, Other than Load Multiples Including the PC
597
Table 16-19 Cycle Timing Behavior of Load Multiples, Where the PC Is in the Register List
598
16.13 RFE and SRS Instructions
599
Table 16-20 RFE and SRS Instructions Cycle Timing Behavior
599
16.14 Synchronization Instructions
600
Table 16-21 Synchronization Instructions Cycle Timing Behavior
600
16.15 Coprocessor Instructions
601
Table 16-22 Coprocessor Instructions Cycle Timing Behavior
601
16.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted Instructions
602
Table 16-23 SVC, BKPT, Undefined, Prefetch Aborted Instructions Cycle Timing Behavior
602
16.17 no Operation
603
16.18 Thumb Instructions
604
Chapter 17 AC Characteristics
605
Processor Timing Diagrams
606
Processor Timing Parameters
607
Table 17-1 Global Signals
607
Table 17-2 AXI Signals
607
Table 17-3 Coprocessor Signals
609
Table 17-4 ETM Interface Signals
609
Table 17-5 Interrupt Signals
609
Table 17-6 Debug Interface Signals
610
Table 17-7 Test Signals
610
Table 17-8 Static Configuration Signals
610
Table 17-9 Trustzone Internal Signals
611
Chapter 18 Introduction to the VFP Coprocessor
612
About the VFP11 Coprocessor
613
Applications
614
Coprocessor Interface
615
VFP11 Coprocessor Pipelines
616
Figure 18-1 FMAC Pipeline
617
Figure 18-2 DS Pipeline
619
Figure 18-3 LS Pipeline
620
Modes of Operation
622
Short Vector Instructions
624
Parallel Execution of Instructions
625
VFP11 Treatment of Branch Instructions
626
Writing Optimal VFP11 Code
627
18.10 VFP11 Revision Information
628
Chapter 19 The VFP Register File
629
About the Register File
630
Figure
630
Register File Internal Formats
631
Figure 19-1 Single-Precision Data Format
631
Figure 19-2 Double-Precision Data Format
632
Decoding the Register File
633
Figure 19-3 Register File Access
633
Loading Operands from ARM11 Registers
634
Table 19-1 VFP11 MCR Instructions
634
Table 19-2 VFP11 MRC Instructions
634
Table 19-3 VFP11 MCRR Instructions
634
Table 19-4 VFP11 MRRC Instructions
635
Maintaining Consistency in Register Precision
636
Data Transfer between Memory and VFP11 Registers
637
Table 19-5 Single-Precision Data Memory Images and Byte Addresses
637
Table 19-6 Double-Precision Data Memory Images and Byte Addresses
637
Access to Register Banks in CDP Operations
638
Figure 19-4 Register Banks
638
Table 19-7 Single-Precision Three-Operand Register Usage
641
Table 19-8 Single-Precision Two-Operand Register Usage
641
Table 19-9 Double-Precision Three-Operand Register Usage
641
Table 19-10 Double-Precision Two-Operand Register Usage
641
Chapter 20 VFP Programmer's Model
642
About the Programmer's Model
643
Compliance with the IEEE 754 Standard
644
Table 20-1 Default Nan Values
645
Table 20-2 Qnan and Snan Handling
646
Armv5Te Coprocessor Extensions
649
Figure 20-1 FMDRR Instruction Format
649
Figure 20-2 FMRRD Instruction Format
650
Figure 20-3 FMSRR Instruction Format
651
Figure 20-4 FMRRS Instruction Format
652
VFP11 System Registers
653
Table 20-3 VFP11 System Registers
653
Table 20-4 Accessing VFP11 System Registers
654
Figure 20-5 Floating-Point System ID Register
654
Table 20-5 FPSID Bit Fields
655
Figure 20-6 Floating-Point Status and Control Register
655
Table 20-6 Encoding of the Floating-Point Status and Control Register
656
Table 20-7 Vector Length and Stride Combinations
657
Table 20-8 Encoding of the Floating-Point Exception Register
658
Figure 20-7 Floating-Point Exception Register
658
Table 20-9 Media and VFP Feature Register 0 Bit Functions
660
Figure 20-8 Media and VFP Feature Register 0 Format
660
Table 20-10 Media and VFP Feature Register 1 Bit Functions
661
Figure 20-9 Media and VFP Feature Register 1 Format
661
Chapter 21 VFP Instruction Execution
662
About Instruction Execution
663
Serializing Instructions
664
Interrupting the VFP11 Coprocessor
665
Forwarding
666
Hazards
667
Operation of the Scoreboards
668
Table 21-1 Single-Precision Source Register Locking
669
Table 21-2 Single-Precision Source Register Clearing
670
Table 21-3 Double-Precision Source Register Locking
671
Table 21-4 Double-Precision Source Register Clearing for One-Cycle Instructions
672
Table 21-5 Double-Precision Source Register Clearing for Two-Cycle Instructions
672
Data Hazards in Full-Compliance Mode
674
Copyright © 2004-2009 ARM Limited. All Rights Reserved
674
Table 21-6 FCMPS-FMSTAT RAW Hazard
674
Table 21-7 FLDM-FADDS RAW Hazard
675
Table 21-8 FLDM-Short Vector FADDS RAW Hazard
675
Table 21-9 FMULS-FADDS RAW Hazard
676
Table 21-10 Short Vector FMULS-FLDMS war Hazard
676
Data Hazards in Runfast Mode
677
Table 21-11 Short Vector FMULS-FLDMS war Hazard in Runfast Mode
677
Resource Hazards
678
Table 21-12 FLDM-FLDS-FADDS Resource Hazard
679
Table 21-13 FLDM-Short Vector FMULS Resource Hazard
679
Table 21-14 Short Vector FDIVS-FADDS Resource Hazard
680
21.10 Parallel Execution
681
Table 21-15 Parallel Execution in All Three Pipelines
682
21.11 Execution Timing
683
Table 21-16 Throughput and Latency Cycle Counts for VFP11 Instructions
683
Chapter 22 VFP Exception Handling
684
About Exception Processing
685
Bounced Instructions
686
Support Code
688
Exception Processing
691
Table 22-1 Exceptional Short Vector FMULD Followed by Load/Store Instructions
692
Table 22-2 Exceptional Short Vector FADDS with a FADDS in the Pretrigger Slot
693
Table 22-3 Exceptional Short Vector FADDD with an FMACS Trigger Instruction
694
Input Subnormal Exception
695
Invalid Operation Exception
696
Table 22-4 Possible Invalid Operation Exceptions
696
Table 22-5 Default Results for Invalid Conversion Inputs
697
Division by Zero Exception
698
Overflow Exception
699
Table 22-6 Rounding Mode Overflow Results
699
Underflow Exception
700
22.10 Inexact Exception
701
22.11 Input Exceptions
702
22.12 Arithmetic Exceptions
703
Table 22-7 LSA and USA Determination
703
Table 22-8 FADD Family Bounce Thresholds
704
Table 22-9 FMUL Family Bounce Thresholds
705
Table 22-10 FDIV Bounce Thresholds
706
Table 22-11 FCVTSD Bounce Thresholds
707
Table 22-12 Single-Precision Float-To-Integer Bounce Thresholds and Stored Results
708
Table 22-13 Double-Precision Float-To-Integer Bounce Thresholds and Stored Results
709
Appendix A Signal Descriptions
711
Global Signals
712
Table A-1 Global Signals
712
Static Configuration Signals
714
Table A-2 Static Configuration Signals
714
Trustzone Internal Signals
715
Table A-3 Trustzone Internal Signals
715
Interrupt Signals, Including VIC Interface
716
Table A-4 Interrupt Signals
716
AXI Interface Signals
717
Table A-5 Port Signal Name Suffixes
717
Table A-6 Instruction Read Port AXI Signal Implementation
718
Table A-7 Data Port AXI Signal Implementation
719
Table A-8 Peripheral Port AXI Signal Implementation
720
Table A-9 DMA Port Signals
721
Coprocessor Interface Signals
722
Table A-10 Core to Coprocessor Signals
722
Table A-11 Coprocessor to Core Signals
722
Debug Interface Signals, Including JTAG
724
Table A-12 Debug Interface Signals
724
ETM Interface Signals
725
Table A-13 ETM Interface Signals
725
Test Signals
726
Table A-14 Test Signals
726
Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
727
About the Differences between the ARM1136JF-S and ARM1176JZF-S Processors
728
Summary of Differences
729
B.2 Summary of Differences
729
Figure
730
Table B-1 TCM for ARM1176JZF-S Processors
732
Table B-2 CP15 C15 Features Common to ARM1136JF-S and ARM1176JZF-S Processors
734
Table B-3 CP15 C15 Only Found in ARM1136JF-S Processors
735
Table C-1 Differences between Issue G and Issue H
738
Figure
751
Figure
752
5
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ARM ARM1176JZF-S Specifications
General
Brand
ARM
Model
ARM1176JZF-S
Category
Computer Hardware
Language
English
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