Level One Memory System
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-11
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For some DMA events an interrupt is generated. If the channel is configured as Non-secure the
nDMAIRQ signal is asserted, otherwise if the channel is configured as Secure the nDMASIRQ
signal is asserted. When an external access caused by the DMA aborts, the processor asserts
nDMAEXTERRIRQ. You can route these output pins to an external interrupt controller for
prioritization and masking. This is the only mechanism to signal the interrupt to the core. For
more information, see c11, DMA Channel Status Register on page 3-117.
Each DMA channel has its own set of Control and Status Registers. The maximum number of
DMA channels that can be defined is architecturally limited to 2. Only 1 DMA channel can be
active at a time. If the other DMA channel has been started, it is queued to start performing
memory operations after the currently active channel has completed. The level one DMA
behaves as a distinct master from the rest of the processor, and the same mechanisms for
handling Shared memory regions must be used if the external addresses being accessed by the
level one DMA system are also accessed by the rest of the processor.
Memory attributes and types on page 6-20 describes these. If a User mode DMA transfer is
performed using an external address that is not marked as Shared, an error is signaled by the
DMA channel. There is no ordering requirement of memory accesses caused by the level one
DMA relative to those generated by reads and writes by the processor, while a channel is
running. When a channel has completed running, all its transactions are visible to all other
observers in the system.
All memory accesses caused by the DMA occur in the order specified by the DMA channel,
regardless of the memory type. If a DMA access is performed to Strongly Ordered memory, see
Memory attributes and types on page 6-20, then a transaction caused by the DMA prevents any
additional transactions being generated by the DMA until the point when the access is complete.
A transaction is complete when it has changed the state of the target location or data has been
returned to the DMA. If the FCSE PID, the Domain Access Control Register, or the page table
mappings are changed, or the TLB is flushed, while a DMA channel is in the Running or Queued
state, then the DMA channel must be stopped.
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