Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-58
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• When FIQs are enabled, and a precise Data Abort occurs at the same time as an FIQ, the
processor enters the Data Abort handler, and proceeds immediately to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Precise Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the worst-case
FIQ latency calculations in a system that uses aborts to support virtual memory.
The FIQ handler must not access any memory that can generate a Data Abort, because the
initial Data Abort exception condition is lost if this happens.
Note
If the data abort is a precise external abort and bit 3 (EA) of SCR is set, the processor enters
Secure Monitor mode where aborts and FIQs are disabled automatically. Therefore, the
processor does not proceed to FIQ vector immediately afterwards.
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