System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-136
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[18]
0x11
Stall because of a full Load Store Unit request queue. This event takes place each
clock cycle when the condition is met. A high incidence of this event indicates the
LSU is often waiting for transactions to complete on the external bus.
[17]
0x10
Explicit external data accesses, Data Cache linefills, Noncacheable, write-through.
[16]
0xF
Main TLB miss.
[15:14]
0xD
Software changed the PC. This event occurs any time the PC is changed by software
and there is not a mode change. For example, a MOV instruction with PC as the
destination triggers this event. Executing an SVC from User mode does not trigger
this event, because it incurs a mode change. If EVENTBUS bit [15] is HIGH, two
software PC changes occurred in this clock cycle and the count increments by two.
[13]
0xC
Data cache write-back. This event occurs once for each half line of four words that
are written back from the cache.
[12]
0xB
Data cache miss. Does not include Cache Operations.
[11]
0xA
Data cache access. Does not include Cache Operations. This event occurs for each
nonsequential access to a cache line, regardless of whether or not the location is
cacheable.
[10]
0x9
Data cache access. Does not include Cache Operations. This event occurs for each
nonsequential access to a cache line, for cacheable locations.
[9:8]
0x7
Instruction executed. If EVENTBUS bit [9] is HIGH, two instructions were executed
in this clock cycle and the count is increments by two.
[7]
0x6
Branch mispredicted.
[6] - Reserved.
[5]
0x5
Branch instruction executed, branch might or might not have changed program flow.
[4]
0x4
Data MicroTLB miss.
[3]
0x3
Instruction MicroTLB miss.
[2]
0x2
Stall because of a data dependency. This event occurs every cycle when the condition
is present.
[1]
0x1
Stall because instruction buffer cannot deliver an instruction. This can indicate an
Instruction Cache miss or an Instruction MicroTLB miss. This event occurs every
cycle when the condition is present.
[0]
0x0
Instruction cache miss.
Note
This event counts all instruction cache misses, including any speculative access that
would be a cache miss. If the instruction that caused a speculative access is not
executed then there might not be a fetch from external memory. This can happen, for
example, if the code branches round the instruction. This means that the value
returned in this counter can be much larger than the number of external memory
accesses caused by instruction cache misses.
- All other values Reserved. Unpredictable behavior.
Table 3-137 Performance monitoring events (continued)
EVNTBUS
bit position
Event
number
Event definition
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