System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-110
ID012310 Non-Confidential, Unrestricted Access
To access the DMA Channel Number Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c11
• CRm set to c2
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c11, c2, 0 ; Read DMA Channel Number Register
MCR p15, 0, <Rd>, c11, c2, 0 ; Write DMA Channel Number Register
3.2.36 c11, DMA enable registers
The purpose of the DMA enable registers is to start, stop or clear DMA transfers for each
channel implemented.
The DMA enable registers are:
• in CP15 c11
• three 32-bit write only registers for each DMA channel common to Secure and
Non-secure worlds
• accessible in user and privileged modes.
The commands that operate through the registers are:
Stop The DMA channel ceases to do memory accesses as soon as possible after the
level one DMA issues the instruction. This acceleration approach cannot be used
for DMA transactions to or from memory regions marked as Device. The DMA
can issue a Stop command when the channel status is Running. The DMA channel
can take several cycles to stop after the DMA issues a Stop instruction. The
channel status remains at Running until the DMA channel stops. The channel
status is set to Complete or Error at the point that all outstanding memory accesses
complete. The Start Address Registers contain the addresses the DMA requires to
restart the operation when the channel stops.
If the Stop command occurs when the channel status is Queued, the channel status
changes to Idle. The Stop command has no effect if the channel status is not
Running or Queued.
c11, DMA Channel Status Register on page 3-117 describes the DMA channel
status.
Start The Start command causes the channel to start DMA transfers. If the other DMA
channel is not in operation the channel status is set to Running on the execution
of a Start command. If the other DMA channel is in operation the channel status
is set to Queued.
A channel is in operation if either:
• its channel status is Queued
• its channel status is Running
• its channel status is Complete or Error, with either the Internal or External
Address Error Status indicating an Error.
c11, DMA Channel Status Register on page 3-117 describes DMA channel status.
Clear The Clear command causes the channel status to change from Complete or Error
to Idle. It also clears:
• all the Error bits for that DMA channel
To Next Page
Loading...
