ARM ARM1176JZF-S - Page 149

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-17
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c9 0 c0 0 Data Cache Lockdown R/W R/W, X 0xFFFFFFF0 page 3-87
1 Instruction Cache Lockdown R/W R/W, X
0xFFFFFFF0 page 3-87
c1 0 Data TCM Region R/W, X R/W, X
0x00000014
f
page 3-89
1 Instruction TCM Region R/W, X R/W, X
0x00000014
g
page 3-91
2 Data TCM Non-secure Control
Access
R/W, X NA 0x00000000 page 3-93
3 Instruction TCM Non-secure
Control Access
R/W, X NA
0x00000000 page 3-94
c2 0 TCM Selection R/W, B R/W
0x00000000 page 3-96
c8 0 Cache Behavior Override
R/W
h
R/W 0x00000000 page 3-97
c10 0 c0 0 TLB Lockdown R/W, X R/W, X
0x00000000 page 3-100
c2 0 Primary Region Memory
Remap Register
R/W, B, X R/W
0x00098AA4 page 3-101
1 Normal Memory Region
Remap Register
R/W, B, X R/W
0x44E048E0 page 3-101
c11 0 c0 0-3 DMA identification and status RO RO, X
0x0000000B
i
page 3-106
c1 0 DMA User Accessibility R/W R/W, X
0x00000000 page 3-107
c2 0 DMA Channel Number R/W, X R/W, X
0x00000000 page 3-109
c3 0-2 DMA enable WO, X WO, X - page 3-110
c4 0 DMA Control R/W, X R/W, X 0x08000000 page 3-112
c5 0 DMA Internal Start Address R/W, X R/W, X - page 3-114
c6 0 DMA External Start Address R/W, X R/W, X - page 3-115
c7 0 DMA Internal End Address R/W, X R/W, X - page 3-116
c8 0 DMA Channel Status RO, X RO, X
0x00000000 page 3-117
c15 0 DMA Context ID R/W R/W, X - page 3-120
c12 0 c0 0 Secure or Non-secure Vector
Base Address
R/W, B, X R/W
0x00000000 page 3-121
1 Monitor Vector Base Address R/W, X NA
0x00000000 page 3-122
c1 0 Interrupt Status RO RO
0x00000000
j
page 3-123
Table 3-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation S type
NS
type
Reset
value
Page