ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-16
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c7 0 c10 0 Clean Entire Data Cache WO, X WO, X - page 3-71
1 Clean Data Cache Line by
MVA
WO WO - page 3-71
2 Clean Data Cache Line by
Index
WO WO - page 3-71
4 Data Synchronization Barrier WO WO -page3-83
5 Data Memory Barrier WO WO -page3-84
6 Cache Dirty Status RO, B RO
0x00000000 page 3-78
c13 1 Prefetch Instruction Cache
Line
WO WO - page 3-71
c14 0 Clean and Invalidate Entire
Data Cache
WO, X WO, X - page 3-71
1 Clean and Invalidate Data
Cache Line by MVA
WO WO - page 3-71
2 Clean and Invalidate Data
Cache Line by Index
WO WO - page 3-71
c8 0 c5 0 Invalidate Instruction TLB
unlocked entries
WO, B WO - page 3-86
1 Invalidate Instruction TLB
entry by MVA
WO, B WO - page 3-86
2 Invalidate Instruction TLB
entry on ASID match
WO, B WO - page 3-86
c8 0 c6 0 Invalidate Data TLB unlocked
entries
WO, B WO - page 3-86
1 Invalidate Data TLB entry by
MVA
WO, B WO - page 3-86
2 Invalidate Data TLB entry on
ASID match
WO, B WO - page 3-86
c7 0 Invalidate unified TLB
unlocked entries
WO, B WO - page 3-86
1 Invalidate unified TLB entry
by MVA
WO, B WO - page 3-86
2 Invalidate unified TLB entry
on ASID match
WO, B WO - page 3-86
Table 3-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation S type
NS
type
Reset
value
Page

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English