Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-49
ID012310 Non-Confidential, Unrestricted Access
• Undefined instruction
• Software Interrupt exception
• External Prefetch Abort on page 2-50
• Internal Prefetch Abort on page 2-50
• External Data Abort on page 2-50
• Internal Data Abort on page 2-51
• Interrupt request (IRQ) exception on page 2-51
• Fast Interrupt Request (FIQ) exception on page 2-52
• Secure Monitor Call Exception on page 2-52.
Reset
When Reset is de-asserted:
/* Enter secure state */
R14_svc = UNPREDICTABLE value
SPSR_svc = UNPREDICTABLE value
CPSR [4:0] = 0b10011 /* Enter supervisor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of Secure Control Register bit[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF0000
else
PC = 0x00000000
Undefined instruction
On an undefined instruction:
/* Non-secure state is unchanged */
R14_und = address of the next instruction after the undefined instruction
SPSR_und = CPSR
CPSR [4:0] = 0b11011 /* Enter undefined Instruction mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
CPSR [9] = Non-secure EE-bit /* store value of NS Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF0004
else
PC = Non_Secure_Base_Address + 0x00000004
Software Interrupt exception
On an SVC:
/* Non-secure state is unchanged */
R14_svc = address of the next instruction after the SVC instruction
SPSR_svc = CPSR
CPSR [4:0] = 0b10011 /* Enter supervisor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
CPSR [9] = Non-secure EE-bit /* store value of NS Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF0008
else
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