Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-10
ID012310 Non-Confidential, Unrestricted Access
2.2.4 Secure Monitor bus
The SECMONBUS exports a set of signals from the core for use in a monitoring block inside
the chip.
Caution
Implementors must ensure that the SECMONBUS signals do not compromise the security of
the processor. The signals provide information for a security monitoring block, that is inside the
SoC, and must not appear outside the chip.
Table 2-2 on page 2-11 lists the signals that appear on the Secure Monitor bus SECMONBUS.
Instruction/Unified TCM
Non-secure Control Access
Register
MCR p15, 0, Rd, c9, c1, 3
Secure Monitor or Privileged when NS=0
Data TCM Region Registers
MCR p15, 0, Rd, c9, c1, 0
All TCM Base Registers for which the
Data TCM Non-secure Control Access
Register = 0
Instruction/Unified TCM Region
Registers
MCR p15, 0, Rd, c9, c1, 1
All TCM Base Registers for which the
Instruction/Unified TCM Non-secure
Control Access Register = 0
Secure Primary Region Remap
Register
MCR p15, 0, Rd, c10, c2, 0
Secure Monitor or Privileged when NS=0
Secure Normal Memory Remap
Register
MCR p15, 0, Rd, c10, c2, 1
Secure Monitor or Privileged when NS=0
Secure Vector Base Register
MCR p15, 0, Rd, c12, c0, 0
Secure Monitor or Privileged when NS=0
Monitor Vector Base Register
MCR p15, 0, Rd, c12, c0, 1
Secure Monitor or Privileged when NS=0
Secure FCSE Register
MCR p15, 0, Rd, c13, c0, 0
Secure Monitor or Privileged when NS=0
Peripheral Port remap Register
MCR p15, 0, Rd, c15, c2, 4
Secure Monitor or Privileged when NS=0
Instruction Cache master valid
register
MCR p15, 3, Rd, c15, c8, {0-7}
Secure Monitor or Privileged when NS=0
Data Cache master valid register
MCR p15, 3, Rd, c15, c12, {0-7}
Secure Monitor or Privileged when NS=0
TLB lockdown Index register
MCR p15, 5, Rd, c15, c4, 2
Secure Monitor or Privileged when NS=0
TLB lockdown VA register
MCR p15, 5, Rd, c15, c5, 2
Secure Monitor or Privileged when NS=0
TLB lockdown PA register
MCR p15, 5, Rd, c15, c6, 2
Secure Monitor or Privileged when NS=0
TLB lockdown Attribute register
MCR p15, 5, Rd, c15, c7, 2
Secure Monitor or Privileged when NS=0
Validation registers
MCR p15, 0, Rd, c15, c9, 0
MCR p15, 0, Rd, c15, c12, {4-7}
MCR p15, 0, Rd, c15, c14, 0
MCR p15, {0-7}, Rd, c15, c13, {0-7}
Secure Monitor or Privileged when NS=0
Table 2-1 Write access behavior for system control processor registers (continued)
Register
Instruction that is Undefined
when CP15SDISABLE=1
Security Condition
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