Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-44
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STR R0, [R8,#AckFinished]
SUBS PC, R14, #4
...
FIQ2handler
SUB R14, R14, #4
SRSFD R13_abt!
CPSIE f, #0x1B ; = Abort mode
STMFD R13!, {R2, R3}
... FIQs are now re-enabled, with original R2, R3, R14, SPSR on stack
... Include code to stack any more registers required, process the interrupt
... and unstack extra registers
LDMFD R13!, {R2, R3}
ADR R14, #VICaddress
CPSID f
STR R0, [R14,#AckFinished]
RFEFD R13!
...
The worst-case interrupt latency for a FIQ1 now occurs if the FIQ1 occurs during an FIQ2
interrupt entry sequence, after it disables FIQs, and is approximately:
• 3 cycles for the pipeline refill for the FIQ2 exception entry sequence
• + 5 cycles to get to and execute the CPSIE instruction that re-enables FIQs
• + 3 cycles to re-enter the FIQ exception
• = 11 cycles.
Note
In the ARMv5 system, the potential additional interrupt latency caused by a long LDM or STM
being in progress when the FIQ is detected was only significant because the memory system was
able to stretch its cycles considerably. Otherwise, it was dwarfed by the number of cycles lost
because of FIQs being disabled at the start of a lower-priority interrupt handler. In ARMv6, this
is still the case, but it is a lot closer.
Alternatives to the example system
Two alternatives to the design in FIQs in the example system in ARMv6 on page 2-43 are:
• The first alternative is not to reserve the FIQ registers for the FIQ1 interrupt, but instead
either to:
— share them out among the various FIQ handlers
The first restricts the registers available to the FIQ1 handler and adds the software
complication of managing a global allocation of FIQ registers to FIQ handlers.
Also, because of the shortage of FIQ registers, it is not likely to be very effective if
there are many FIQ handlers.
— require the FIQ handlers to treat them as normal callee-save registers.
The second adds a number of cycles of loading important addresses and variable
values into the registers to each FIQ handler before it can do any useful work. That
is, it increases the effective FIQ latency by a similar number of cycles.
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