Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-46
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When a Prefetch Abort occurs, the processor marks the prefetched instruction as invalid, but
does not take the exception until the instruction is to be executed. If the instruction is not
executed, for example because a branch occurs while it is in the pipeline, the abort does not take
place.
After dealing with the cause of the abort, the handler executes the following instruction
irrespective of the processor operating state:
SUBS PC,R14_abt,#4
This action restores both the PC and the CPSR, and retries the aborted instruction.
Data Abort
Data Abort on the processor can be precise or imprecise. Precise Data Aborts are those
generated after performing an instruction side CP15 operation, and all those generated by the
MMU:
• alignment faults
• translation faults
• access bit faults
• domain faults
• permission faults.
Data Aborts that occur because of watchpoints are imprecise in that the processor and system
state presented to the abort handler is the processor and system state at the boundary of an
instruction shortly after the instruction that caused the watchpoint, but before any following
load/store instruction. Because the state that is presented is consistent with an instruction
boundary, these aborts are restartable, even though they are imprecise.
Errors that cause externally generated Data Aborts might be precise or imprecise. Two separate
FSR encodings indicate if the external abort is precise or imprecise:
• all external aborts to loads when the CP15 Register 1 FI bit, bit 21, is set are precise
• all external aborts to loads or stores to Strongly Ordered memory are precise
• all external aborts to loads to the Program Counter or the CSPR are precise
• all external aborts on the load part of a SWP are precise
• all other external aborts are imprecise.
External aborts are supported on cacheable locations. The abort is transmitted to the processor
only if a word requested by the processor had an external abort.
Precise Data Aborts
A precise Data Abort is signaled when the abort exception enables the processor and system
state presented to the abort handler to be consistent with the processor and system state when
the aborting instruction was executed. With precise Data Aborts, the restarting of the processor
after the cause of the abort has been rectified is straightforward.
The ARM1176JZF-S processor implements the base restored Data Abort model, that differs
from the base updated Data Abort model implemented by the ARM7TDMI-S processor.
With the base restored Data Abort model, when a Data Abort exception occurs during the
execution of a memory access instruction, the base register is always restored by the processor
hardware to the value it contained before the instruction was executed. This removes the
requirement for the Data Abort handler to unwind any base register update, that might have been
specified by the aborted instruction. This simplifies the software Data Abort handler. See ARM
Architecture Reference Manual for more details.
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