ARM ARM1176JZF-S - Page 19

List of Figures
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xix
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Figure 3-64 DMA Context ID Register format ............................................................................................ 3-120
Figure 3-65 Secure or Non-secure Vector Base Address Register format ................................................ 3-121
Figure 3-66 Monitor Vector Base Address Register format ........................................................................ 3-122
Figure 3-67 Interrupt Status Register format .............................................................................................. 3-124
Figure 3-68 FCSE PID Register format ...................................................................................................... 3-126
Figure 3-69 Address mapping with the FCSE PID Register ....................................................................... 3-127
Figure 3-70 Context ID Register format ..................................................................................................... 3-128
Figure 3-71 Peripheral Port Memory Remap Register format .................................................................... 3-130
Figure 3-72 Secure User and Non-secure Access Validation Control Register format .............................. 3-132
Figure 3-73 Performance Monitor Control Register format ........................................................................ 3-133
Figure 3-74 System Validation Counter Register format for external debug request counter .................... 3-141
Figure 3-75 System Validation Cache Size Mask Register format ............................................................. 3-145
Figure 3-76 TLB Lockdown Index Register format ..................................................................................... 3-149
Figure 3-77 TLB Lockdown VA Register format ......................................................................................... 3-149
Figure 3-78 TLB Lockdown PA Register format ......................................................................................... 3-150
Figure 3-79 TLB Lockdown Attributes Register format .............................................................................. 3-151
Figure 4-1 Load unsigned byte ..................................................................................................................... 4-6
Figure 4-2 Load signed byte ......................................................................................................................... 4-6
Figure 4-3 Store byte .................................................................................................................................... 4-7
Figure 4-4 Load unsigned halfword, little-endian ......................................................................................... 4-7
Figure 4-5 Load unsigned halfword, big-endian ........................................................................................... 4-8
Figure 4-6 Load signed halfword, little-endian ............................................................................................. 4-8
Figure 4-7 Load signed halfword, big-endian ............................................................................................... 4-9
Figure 4-8 Store halfword, little-endian ........................................................................................................ 4-9
Figure 4-9 Store halfword, big-endian ........................................................................................................ 4-10
Figure 4-10 Load word, little-endian ............................................................................................................. 4-10
Figure 4-11 Load word, big-endian .............................................................................................................. 4-11
Figure 4-12 Store word, little-endian ............................................................................................................ 4-11
Figure 4-13 Store word, big-endian .............................................................................................................. 4-12
Figure 6-1 Memory ordering restrictions .................................................................................................... 6-24
Figure 6-2 Translation table managed TLB fault checking sequence part 1 .............................................. 6-30
Figure 6-3 Translation table managed TLB fault checking sequence part 2 .............................................. 6-31
Figure 6-4 Backwards-compatible first-level descriptor format .................................................................. 6-37
Figure 6-5 Backwards-compatible second-level descriptor format ............................................................. 6-38
Figure 6-6 Backwards-compatible section, supersection, and page translation ........................................ 6-38
Figure 6-7 ARMv6 first-level descriptor formats with subpages disabled ................................................... 6-39
Figure 6-8 ARMv6 second-level descriptor format ..................................................................................... 6-40
Figure 6-9 ARMv6 section, supersection, and page translation ................................................................. 6-41
Figure 6-10 Creating a first-level descriptor address ................................................................................... 6-44
Figure 6-11 Translation for a 1MB section, ARMv6 format .......................................................................... 6-46
Figure 6-12 Translation for a 1MB section, backwards-compatible format .................................................. 6-46
Figure 6-13 Generating a second-level page table address ........................................................................ 6-47
Figure 6-14 Large page table walk, ARMv6 format ...................................................................................... 6-48
Figure 6-15 Large page table walk, backwards-compatible format .............................................................. 6-49
Figure 6-16 4KB small page or 1KB small subpage translations, backwards-compatible format ................ 6-50
Figure 6-17 4KB extended small page translations, ARMv6 format ............................................................. 6-51
Figure 6-18 4KB extended small page or 1KB extended small subpage translations,
backwards-compatible format ................................................................................................... 6-52
Figure 7-1 Level one cache block diagram .................................................................................................. 7-4
Figure 8-1 Level two interconnect interfaces ................................................................................................ 8-2
Figure 8-2 Channel architecture of reads ..................................................................................................... 8-8
Figure 8-3 Channel architecture of writes .................................................................................................... 8-8
Figure 8-4 Swizzling of data and strobes in BE-32 big-endian configuration ............................................. 8-38
Figure 9-1 Processor clocks with no IEM .........................................................................................
............ 9-3
Figure 9-2 Read latency with no IEM ........................................................................................................... 9-4
Figure 9-3 Processor clocks with IEM .......................................................................................................... 9-6
Figure 9-4 Processor synchronization with IEM ........................................................................................... 9-6
Figure 9-5 Read latency with IEM ................................................................................................................ 9-8
Figure 9-6 Power-on reset .......................................................................................................................... 9-10
Figure 10-1 IEM structure ............................................................................................................................. 10-8