Program Flow Prediction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 5-3
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• Main TLB context ID changes
• Global instruction cache invalidation
• Switches by the integer core from Non-secure to Secure state.
When the processor switches from the Secure to the Non-secure state the Secure Monitor code
is responsible for flushing the BTAC if necessary.
The PU prefetches all instruction types regardless of the state of the integer core. That is, it
performs prefetches in ARM state, Thumb state, and Jazelle state. However the rate at which the
PU is drained is state-dependent, and the functioning of the branch prediction hardware is a
function of the state. Branch prediction is performed in all three states, but branch folding
operates only in ARM and Thumb states.
The PU is responsible for fetching the instruction stream as dictated by:
• the Program Counter
• the dynamic branch predictor
• static prediction results in the integer core
• procedure calls and returns signaled by the Return Stack residing in the integer core
• exceptions, instruction aborts, and interrupts signaled by the integer core.
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