Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-8
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Supersections, sections, and large pages are supported to permit mapping of a large region of
memory while using only a single entry in a TLB. If no mapping for an address is found within
the TLB, then the translation table is automatically read by hardware, if not disabled with PD0
and PD1 bits in the TTB Control register, and a mapping is placed in the TLB. See Hardware
page table translation on page 6-36 for more details.
6.3.2 Virtual to physical translation mapping restrictions
You can use the processor MMU architecture in conjunction with virtually indexed physically
tagged caches. For details of any mapping page table restrictions for virtual to physical
addresses see Restrictions on page table mappings page coloring on page 6-41.
6.3.3 Tightly-Coupled Memory
There are no page table restrictions for mappings to the Tightly-Coupled Memory (TCM). For
details of the TCM see Tightly-coupled memory on page 7-7.
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