Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-10
ID012310 Non-Confidential, Unrestricted Access
Note
By default, the PRRR and NMRR registers are reset to that all accesses are treated
as Strongly Ordered.
The other parameters of the MMU behavior when disabled, independent of the TEX remap
configuration, are:
• No memory access permission or Access bit checks are performed, and no aborts are
generated by the MMU.
• The physical address for every access is equal to its virtual address. This is known as a flat
address mapping.
• The NS attribute for the target memory region is equal to the state, Secure or Non-secure,
of the request, that is Secure requests are considered to target Secure memory.
• The FCSE PID Should Be Zero when the MMU is disabled. This is the reset value of the
FCSE PID. If the MMU is to be disabled the FCSE PID must be cleared.
• All CP15 MMU and cache operations can be executed even when the MMU is disabled.
• Accesses to the TCMs work as normal if the TCMs are enabled.
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