Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-22
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6.7.2 Device memory attribute
The Device memory attribute is defined for memory locations where an access to the location
can cause side effects, or where the value returned for a load can vary depending on the number
of loads performed. Memory-mapped peripherals and I/O locations are typical examples of
areas of memory that you must mark as Device. The marking of a region of memory as Device
is performed on a per-page basis in the MMU.
Accesses to memory-mapped locations that have side effects that apply to memory locations
that are Normal memory might require Memory Barriers to ensure correct execution. An
example where this might be an issue is the programming of the control registers of a memory
controller while accesses are being made to the memories controlled by the controller.
Instruction fetches must not be performed to areas of memory containing read-sensitive devices,
because there is no ordering requirement between instruction fetches and explicit accesses.
As a result, instruction fetches from such devices can result in Unpredictable behavior. Up to 64
bytes can be prefetched sequentially ahead of the current instruction being executed. To enable
this, read-sensitive devices must be located in memory in such a way to enable this prefetching.
Explicit accesses from the processor to regions of memory marked as Device occur at the size
and order defined by the instruction. The number of location accesses is specified by the
program. Repeat accesses to such locations when there is only one access in the program, that
is the accesses are not restartable, are not possible in the processor.
An example of where a repeat access might be required is before and after an interrupt to enable
the interrupt to abandon a slow access. You must ensure these optimizations are not performed
on regions of memory marked as Device. If a memory operation that causes multiple
transactions, such as an LDM or an unaligned memory access, crosses a 4KB address boundary,
then it can perform more accesses than are specified by the program, regardless of one or both
of the areas being marked as Device.
For this reason, accesses to volatile memory devices must not be made using single instructions
that cross a 4KB address boundary. This restriction is expected to cause restrictions to the
placing of such devices in the memory map of a system, rather than to cause a compiler to be
aware of the alignment of memory accesses. In addition, address locations marked as Device are
not held in a cache.
Shared memory attribute
Regions of Memory marked as Device are also distinguished by the Shared attribute in the
MMU. These memory regions can be marked as:
• Shared Device
• Non-Shared Device.
Explicit accesses to memory with each of the sets of attributes occur in program order relative
to other explicit accesses to the same set of attributes. All explicit accesses to memory marked
as Device must correspond to the ordering requirements of accesses that Ordering requirements
for memory accesses on page 6-23 describes. The marking of the same memory location as
being Shared Device and Non-Shared Device in an MMU, for example by the use of synonyms
in a virtual to physical address mapping, results in Unpredictable behavior but this does not
break security.
An example of an implementation where the Shared attribute is used to distinguish memory
accesses is an implementation that supports a local bus for its private peripherals, while system
peripherals are situated on the main system bus. Such a system can have more predictable access
times for local peripherals such as watchdog timers or interrupt controllers. For shared device
memory, the data of a write is visible to all observers before the end of a Data Synchronization
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