Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-12
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The first level of branch prediction is dynamic, through a 128-entry Branch Target Address
Cache (BTAC). If the PC of a branch matches an entry in the BTAC, the processor uses the
branch history and the target address to fetch the new instruction stream.
The processor might remove dynamically predicted branches from the instruction stream, and
might execute such branches in zero cycles.
If the address mappings are changed, the BTAC must be flushed. A BTAC flush instruction is
provided in the CP15 coprocessor.
The processor uses static branch prediction to manage branches not matched in the BTAC. The
static branch predictor makes a prediction based on the direction of the branches.
1.5.4 Memory system
The level-one memory system provides the core with:
• separate instruction and data caches
• separate instruction and data Tightly-Coupled Memories
• 64-bit datapaths throughout the memory system
• virtually indexed, physically tagged caches
• memory access controls and virtual memory management
• support for four sizes of memory page
• two-channel DMA into TCMs
• I-fetch, D-read/write interface, compatible with multi-layer AMBA AXI
• 32-bit dedicated peripheral interface
• export of memory attributes for second-level memory system.
The following sections describe the memory system in more detail:
• Instruction and data caches
• Cache power management on page 1-13
• Instruction and data TCM on page 1-13
• TCM DMA engine on page 1-14
• DMA features on page 1-14
• Memory Management Unit on page 1-14.
Instruction and data caches
The core provides separate instruction and data caches. The cache has the following features:
• Independent configuration of the instruction and data cache during synthesis to sizes
between 4KB and 64KB.
• 4-way set-associative instruction and data caches. You can lock each way independently.
• Pseudo-random or round-robin replacement.
• Eight word cache line length.
• The MicroTLB entry determines whether cache lines are write-back or write-through.
• Ability to disable each cache independently, using the system control coprocessor.
• Data cache misses that are non-blocking. The processor supports up to three outstanding
data cache misses.
• Streaming of sequential data from LDM and LDRD operations, and sequential instruction
fetches.
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