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Introduction

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1.5.5 AMBA AXI interface

The bus interface provides high bandwidth connections between the processor, second level

caches, on-chip RAM, peripherals, and interfaces to external memory.

There are separate bus interfaces for:

• instruction fetch, 64-bit data

• data read/write, 64-bit data

• peripheral access, 32-bit data

• DMA, 64-bit data.

All interfaces are AMBA AXI compatible. This enables them to be merged in smaller systems.

Additional signals are provided on each port to support second-level cache.

The ports support the following bus transactions:

Instruction fetch

Servicing instruction cache misses and noncacheable instruction fetches.

Data read/write

Servicing data cache misses, hardware handled TLB misses, cache eviction and

noncacheable data reads and writes.

DMA Servicing the DMA engine for writing and reading the TCMs. This behaves as a

single bidirectional port.

These ports enable several simultaneous outstanding transactions, providing:

• high performance from second-level memory systems that support parallelism

• high use of pipelined and multi-page memories such as SDRAM.

The following sections describe the AMBA AXI interface in more detail:

• Bus clock speeds

• Unaligned accesses

• Mixed-endian support

• Write buffer on page 1-17

• Peripheral port on page 1-17.

Bus clock speeds

The bus interface ports operate synchronously to the CPU clock if IEM is not implemented.

Unaligned accesses

The core supports unaligned data access. Words and halfwords can align to any byte boundary.

This enables access to compacted data structures with no software overhead. This is useful for

multi-processor applications and reducing memory space requirements.

The Bus Interface Unit (BIU) automatically generates multiple bus cycles for unaligned

accesses.

Mixed-endian support

The core provides the option of switching between little-endian and byte invariant big endian

data access modes. This means the core can share data with big-endian systems, and improves

the way the core manages certain types of data.

ARM ARM1176JZF-S User Manual

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