Power Control
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 10-4
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Note
The core clock does not stop when the core is prepared for debug activity, that is, when either
TCK or JTAGSYNCBYPASS is high.
10.2.3 Shutdown mode
Shutdown mode has the entire device powered down, and you must externally save all state,
including cache and TCM state. The processor is returned to Run mode by the assertion of
Reset. The state saving must be performed with interrupts disabled, and finish with a Data
Synchronization Barrier operation. When all the state of the processor is saved the processor
must execute a Wait For Interrupt operation. The signal STANDBYWFI is asserted to indicate
that the processor can enter Shutdown mode.
10.2.4 Dormant mode
Dormant mode enables the core to be powered down, leaving the caches and the
Tightly-Coupled Memory (TCM) powered up and maintaining their state.
The software visibility of the Cache Master Valid bits and the TLB lockdown entries is provided
to enable an implementation to be extended for Dormant mode.
The processor includes a placeholder that enables you to include the clamping logic necessary
for the full implementation of Dormant mode.
Considerations for Dormant mode
Dormant mode is only partially supported on the processor, because care is required in
implementing this on a standard synthesizable flow. The RAM blocks that are to remain
powered up must be implemented on a separate power domain, and there is a requirement to
clamp all of the inputs to the RAMs to a known logic level, with the chip enable being held
inactive. This clamping is not implemented in gates as part of the default synthesis flow because
it contributes to a critical path. The RAMCLAMP input is provided to drive this clamping.
Basic clamps are instantiated in the placeholder. They can be changed to explicit gates in the
RAM power domain, or pull-down transistors that clamp the values when the core is powered
down. For implementation details, see the ARM1176JZF-S and ARM1176JZ-S Implementation
Guide.
The RAM blocks that must remain powered up in Dormant mode, if it is implemented, are:
• all Data RAMs associated with the cache and tightly-coupled memories
• all TagRAMs associated with the cache
• all Valid RAMs and Dirty RAMs associated with the cache.
The states of the Branch Target Address Cache and the associative region of the TLB are not
maintained on entry into Dormant mode.
Implementations of the processor can optionally disable RAMs associated with the main TLB,
so that a trade-off can be made between Dormant mode leakage power and the recovery time.
Before entering Dormant mode, the state of the processor, excluding the contents of the RAMs
that remain powered up in dormant mode, must be saved to external memory. These state saving
operations must ensure that the following occur:
• All ARM registers, including CPSR and SPSR registers are saved.
• Any DMA operations in progress are stopped.
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