Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-12
ID012310 Non-Confidential, Unrestricted Access
The following DSCR bits affect the operation of other scan chains:
DSCR[30:29] rDTRfull and wDTRfull flags. These indicate the status of the rDTR and
wDTR registers. They are copies of the rDTRempty, NOT rDTRfull, and
wDTRfull bits that the DBGTAP debugger sees in scan chain 5.
DSCR[13] Execute ARM instruction enable bit. This bit enables the mechanism used
for executing instructions in Debug state. It changes the behavior of the
rDTR and wDTR registers, the sticky precise Data Abort bit, rDTRempty,
wDTRfull, and InstCompl flags. See Scan chain 5 on page 14-15.
DSCR[6] Sticky precise Data Abort flag. If the core is in Debug state and the
DSCR[13] execute ARM instruction enable bit is HIGH, then this flag is
set on precise Data Aborts. See CP14 c1, Debug Status and Control
Register (DSCR) on page 13-7.
Note
Unlike DSCR[6], DSCR [7] sticky imprecise Data Aborts flag and
DSCR[8] sticky Undefined bits do not affect the operation of the other
scan chains.
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