Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-33
ID012310 Non-Confidential, Unrestricted Access
2. Cache and MMU restoration must be done here. This includes writing the saved registers
back to CP15.
3. Ensure that rDTR and wDTR are empty:
ITRSE ; select the ITR and EXTEST
INST MCR p14,0,R0,c0,c5,0 ; instruction to copy R0 into
; CP14 debug register c5
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1 ; wait until the instruction ends
SCAN_N 5
INTEST
DATA 0x0 Valid wDTR
4. If the wDTR did not contain any valid data on Debug state entry go to step 5. Otherwise,
restore wDTRfull and wDTR, uses R0 as a temporary register, in two steps.
a. Load the saved wDTR contents into R0 using the standard sequence of Writing a
current mode ARM register in the range R0-R14 on page 14-34. Now scan chain 5
and EXTEST are selected
b. Transfer R0 into wDTR:
ITRSEL ; select the ITR and EXTEST
INST MCR p14,0,R0,c0,c5,0 ; instruction to copy R0 into
; CP14 debug register c5
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1 ; wait until the instruction ends
5. Restore CPSR using the standard CPSR writing sequence that Writing the CPSR/SPSR on
page 14-35 describes.
6. Restore the PC using the standard sequence of Writing the PC on page 14-36.
7. Restore R0 using the standard sequence of Writing a current mode ARM register in the
range R0-R14 on page 14-34. Now scan chain 5 and EXTEST are selected.
8. Restore the DSCR with the DSCR[13] execute ARM instruction enable bit clear, so no
more instructions can be issued to the core:
SCAN_N 1 ; select DSCR
EXTEST
DATA modifiedDSCR ; modifiedDSCR equals the saved contents
; of the DSCR with bit DSCR[13] clear
9. If the rDTR did not contain any valid data on Debug state entry, go to step 10. Otherwise,
restore the rDTR and rDTRempty flag:
SCAN_N 5 ; select DTR
EXTEST
DATA Saved_rDTR ; rDTRempty bit is automatically cleared
; as a result of this action
10. Restart processor:
RESTART
11. Wait until the core is restarted:
SCAN_N 1 ; select DSCR
INTEST
LOOP
DATAOUT readDSCR
UNTIL readDSCR[1]==1 ; until Core Restarted bit is set
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