Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-8
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16.3.3 Example interlocks
Most data processing instructions are single-cycle and can be executed back-to-back without
interlock cycles, even if there are data dependencies between them. The exceptions to this are
when the Shifter or Register controlled shifts are used.
Shifter
The shifter is in a separate pipeline stage from the ALU. A register required by the shifter is an
Early Reg and requires an additional cycle of result availability before use. For example, the
following sequence introduces a one-cycle interlock, and takes three cycles to execute:
ADD R1,R2,R3
ADD R4,R5,R1 LSL #1
The second source register, that is not shifted, does not incur an extra data dependency check.
Therefore, the following sequence takes two cycles to execute:
ADD R1,R2,R3
ADD R4,R1,R9 LSL #1
Register controlled shifts
Register controlled shifts take two cycles to execute:
• the register containing the shift distance is read in the first cycle
• the shift is performed in the second cycle
• The final operand is not required until the ALU stage for the second cycle.
Because a shift distance is required, the register containing the shift distance is an Early Reg and
incurs an extra interlock penalty. For example, the following sequence takes four cycles to
execute:
ADD R1, R2, R3
ADD R4, R2, R4, LSL R1
MOV <cond> pc, <Rn>, <Rm>, LSL #<immed>
6-7
a
- - - Conditional MOV to PC, with a
shifted source register
MOV pc, <Rn>, <Rm>, LSL <Rs>
7
<Rs> <Rn>
- MOV to pc, with a register
controlled shifted source
register
ADD pc, <Rd>, <Rm>
7 - - - Normal case to PC
ADD pc, <Rn>, <Rm>, LSL #<immed>
7
<Rm>
- - Requires a shifted source
register
ADD pc, <Rn>, <Rm>, LSL <Rs>
8
<Rs> <Rn>
- Requires a register controlled
shifted source register
a. If the instruction is conditional and passes conditional checks it takes MAX (MaxCycles - FlagCycleDistance, MinCycles), If
the instruction is unconditional it takes Min Cycles.
Table 16-5 Data Processing Instruction cycle timing behavior if destination is the PC (continued)
Example Instruction
Cycle
s
Earl
y
Reg
Late
Reg
Result
latency
Comment
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