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Introduction to the VFP coprocessor

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Arithmetic exceptions on page 22-20 describes the conditions when the VFP11 coprocessor

traps to support code.

18.5.2 Flush-to-zero mode

Setting the FZ bit, FPSCR[24], enables flush-to-zero mode and increases performance on very

small inputs and results. In flush-to-zero mode, the VFP11 coprocessor treats all subnormal

input operands of arithmetic CDP operations as positive zeros in the operation. Exceptions that

result from a zero operand are signaled appropriately. FABS, FNEG, and FCPY are not

considered arithmetic CDP operations and are not affected by flush-to-zero mode. A result that

is tiny, as the IEEE 754 standard describes, for the destination precision is smaller in magnitude

than the minimum normal value before rounding and is replaced with a positive zero. The IDC

flag, FPSCR[7], indicates when an input flush occurs. The UFC flag, FPSCR[3], indicates when

a result flush occurs.

18.5.3 Default NaN mode

Setting the DN bit, FPSCR[25], enables default NaN mode. In default NaN mode, the result of

any operation that involves an input NaN or generated a NaN result returns the default NaN.

Propagation of the fraction bits is maintained only by FABS, FNEG, and FCPY operations, all

other CDP operations ignore any information in the fraction bits of an input NaN. See NaN

handling on page 20-4 for a description of default NaNs.

18.5.4 RunFast mode

RunFast mode is the combination of the following conditions:

• the VFP11 coprocessor is in flush-to-zero mode

• the VFP11 coprocessor is in default NaN mode

• all exception enable bits are cleared.

In RunFast mode the VFP11 coprocessor:

• processes subnormal input operands as positive zeros

• processes results that are tiny before rounding, that is, between the positive and negative

minimum normal values for the destination precision, as positive zeros

• processes input NaNs as default NaNs

• returns the default result specified by the IEEE 754 standard for overflow, division by

zero, invalid operation, or inexact operation conditions fully in hardware and without

additional latency

• processes all operations in hardware without trapping to support code.

RunFast mode enables the programmer to write code for the VFP11 coprocessor that runs in a

determinable time without support code assistance, regardless of the characteristics of the input

data. In RunFast mode, no user exception traps are available. However, the exception flags in

the FPSCR register are compliant with the IEEE 754 standard for Inexact, Overflow, Invalid

Operation, and Division by Zero exceptions. The underflow flag is modified for flush-to-zero

mode. Each of these flags is set by an exceptional condition and can by cleared only by a write

to the FPSCR register.

ARM ARM1176JZF-S User Manual

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