To Next Page

To Previous Page

VFP Programmer’s Model

ID012310 Non-Confidential, Unrestricted Access

In flush-to-zero mode, results that are tiny before rounding, as the IEEE 754 standard describes,

are flushed to a positive zero, and the UFC flag, FPSCR[3], is set. Support code is not involved.

See Part C of the ARM Architecture Reference Manual for information on flush-to-zero mode.

When the VFP11 coprocessor is not in flush-to-zero mode, any operation with a risk of

producing a tiny result bounces to support code. If the operation does not produce a tiny result,

it returns the computed result, and the UFC flag, FPSCR[3], is not set. The IXC flag, FPSCR[4],

is set if the operation is inexact. If the operation produces a tiny result, the result is a subnormal

or zero value, and the UFC flag, FPSCR[3], is set. See Underflow exception on page 22-17 for

more information on underflow handling.

Exceptions

Exceptions are taken in the VFP11 coprocessor in an imprecise manner. When exception

processing begins, the states of the ARM11 processor and the VFP11 coprocessor might not be

the same as when the exception occurred. Exceptional instructions cause the VFP11

coprocessor to enter the exceptional state, and the next VFP11 instruction triggers exception

processing. After the issue of the exceptional instruction and before exception processing

begins, non-VFP11 instructions and some VFP11 instructions can be executed and retired. Any

source registers involved in the exceptional instruction are preserved, and the destination

not set, the support code returns to the program flow at the point of the trigger instruction after

processing the exception. If the detected exception enable bit is set, and a user trap handler is

installed, the support code passes control to the user trap handler. If the exception is overflow or

underflow, the intermediate result specified by the IEEE 754 standard is made available to the

user trap handler.

ARM ARM1176JZF-S User Manual

Questions and Answers: