Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-15
ID012310 Non-Confidential, Unrestricted Access
The following causes override the behavior specified in the Table 4-3 on page 4-14:
• An LDR instruction that loads the PC, has Addr[1:0] != b00, and is specified in the table
as having Normal behavior instead has Unpredictable behavior.
0 1 bxxx Halfword Normal Halfword[Addr]
0 1 bxx0 HWSync Normal Halfword[Addr]
0 1 bxx1 HWSync Alignment fault
0 1 bxxx Wload,
WStore
Normal Word[Addr]
0 1 bx00 WSync,
Multi-word,
Two-word
Normal Word[Addr]
0 1 bxx1, bx1x WSync,
Multi-word,
Two-word
Alignment fault - -
0 1 b000 DWSync Normal Word[Addr]
0 1 bxx1,
bx1x, b1xx
DWSync Alignment fault -
1 x - - - - Full alignment faulting
1 x bxxx Byte, BSync Normal Byte[Addr]
1 x bxx0 Halfword,
HWSync
Normal Halfword[Addr]
1 x bxx1 Halfword,
HWSync
Alignment fault -
1 x bx00 WLoad,
WStore,
WSync,
Multi-word
Normal Word[Addr]
1 x bxx1, bx1x WLoad,
WStore,
WSync,
Multi-word
Alignment fault -
1 x b000 Two-word Normal Word[Addr]
1 0 b100 Two-word Alignment fault -
1 1 b100 Two-word Normal Word[Addr]
1 x bxx1, bx1x Two-word Alignment fault -
1 x b000 DWSync Normal Word[Addr]
1 x bxx1,
bx1x, b1xx
DWSync Alignment fault -
Table 4-3 Unalignment fault occurrence when access behavior is architecturally unpredictable (continued)
A U Addr[2:0]
Access
types
Architectural
Behavior
Memory accessed Note
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