Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-16
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The reason why this applies only to LDR is that most other load instructions are
Unpredictable regardless of alignment if the PC is specified as their destination register.
The exceptions are ARM LDM and RFE instructions, and Thumbs POP instruction. If the
instruction for them is Addr[1:0] != b00, the effective address of the transfer has its two
least significant bits forced to 0 if A is set 0 and U is set to 0. Otherwise the behavior
specified in Table 4-3 on page 4-14 is either Unpredictable or Alignment Fault regardless
of the destination register.
• Any WLoad, WStore, WSync, Two-word, or Multi-word instruction that accesses device
memory, has Addr[1:0] != b00, and Table 4-3 on page 4-14 lists them as having Normal
behavior instead has Unpredictable behavior.
• Any Halfword instruction that accesses device memory, has Addr[0] != 0, and is specified
in the table as having Normal behavior instead has Unpredictable behavior.
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