Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-35
ID012310 Non-Confidential, Unrestricted Access
Status register
handling
Move SPSR to register
MRS{cond} <Rd>, SPSR
Move CPSR to register
MRS{cond} <Rd>, CPSR
Move register to SPSR
MSR{cond} SPSR_{field}, <Rm>
Move register to CPSR
MSR{cond} CPSR_{field}, <Rm>
Move immediate to SPSR flags
MSR{cond} SPSR_{field}, #<immed_8r>
Move immediate to CPSR flags
MSR{cond} CPSR_{field}, #<immed_8r>
Load Word
LDR{cond} <Rd>, <a_mode2>
Word with User mode privilege
LDR{cond}T <Rd>, <a_mode2P>
PC as destination, branch and
exchange
LDR{cond} R15, <a_mode2P>
Byte
LDR{cond}B <Rd>, <a_mode2>
Byte with User mode privilege
LDR{cond}BT <Rd>, <a_mode2P>
Byte signed
LDR{cond}SB <Rd>, <a_mode3>
Halfword
LDR{cond}H <Rd>, <a_mode3>
Halfword signed
LDR{cond}SH <Rd>, <a_mode3>
Doubleword
LDR{cond}D <Rd>, <a_mode3>
Return from exception
RFE<a_mode4> <Rn>{!}
Load multiple Stack operations
LDM{cond}<a_mode4L> <Rn>{!}, <reglist>
Increment before
LDM{cond}IB <Rn>{!}, <reglist>{^}
Increment after
LDM{cond}IA <Rn>{!}, <reglist>{^}
Decrement before
LDM{cond}DB <Rn>{!}, <reglist>{^}
Decrement after
LDM{cond}DA <Rn>{!}, <reglist>{^}
Stack operations and restore CPSR
LDM{cond}<a_mode4> <Rn>{!}, <reglist+pc>^
User registers
LDM{cond}<a_mode4> <Rn>{!}, <reglist>^
Soft preload Memory system hint
In Non-secure this instruction
behaves like a
NOP
PLD <a_mode2>
Store Word
STR{cond} <Rd>, <a_mode2>
Word with User mode privilege
STR{cond}T <Rd>, <a_mode2P>
Byte
STR{cond}B <Rd>, <a_mode2>
Byte with User mode privilege
STR{cond}BT <Rd>, <a_mode2P>
Halfword
STR{cond}H <Rd>, <a_mode3>
Doubleword
STR{cond}D <Rd>, <a_mode3>
Store return state
SRS<a_mode4> <mode>{!}
Table 1-7 ARM instruction set summary (continued)
Operation Assembler