ARM ARM1176JZF-S - Page 62

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-36
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Store multiple Stack operations STM{cond}<a_mode4S> <Rn>{!}, <reglist>
User registers STM{cond}<a_mode4S> <Rn>, <reglist>^
Increment before STM{cond}IB, <Rn>{!}, <reglist>{^}
Increment after STM{cond}IA, <Rn>{!}, <reglist>{^}
Decrement before STM{cond}DB, <Rn>{!}, <reglist>{^}
Decrement after STM{cond}DA, <Rn>{!}, <reglist>{^}
Swap Word SWP{cond} <Rd>, <Rm>, [<Rn>]
Byte SWP{cond}B <Rd>, <Rm>, [<Rn>]
Change state Change processor state CPS<effect> <iflags>{, <mode>}
Change processor mode CPS <mode>
Change endianness SETEND <endian_specifier>
NOP-compatible
hints
No Operation NOP{<cond>}
YIELD{<cond>}
Byte-reverse Byte-reverse word REV{cond} <Rd>, <Rm>
Byte-reverse halfword REV16{cond} <Rd>, <Rm>
Byte-reverse signed halfword REVSH{cond} <Rd>, <Rm>
Synchronization
primitives
Load exclusive LDREX{cond} <Rd>, [<Rn> ]
Store exclusive
STREX{cond} <Rd>, <Rm>, [<Rn>]
Load Byte Exclusive
LDREXB{cond} <Rxf>, [<Rbase>]
Load Halfword Exclusive
LDREXH{cond} <Rd>, [<Rn>]
Load Doubleword Exclusive
LDREXD{cond} <Rd>, [<Rn>]
Store Byte Exclusive
STREXB{cond} <Rd>, <Rm>, [<Rn>]
Store Halfword Exclusive
STREXH{cond} <Rd>, <Rm>, [<Rn>]
Store Doubleword Exclusive
STREXD{cond} <Rd>, <Rm>, [<Rn>]
Clear Exclusive
CLREX
Coprocessor Data operations CDP{cond} <cp_num>, <op1>, <CRd>, <CRn>, <CRm>{, <op2>}
Move to ARM reg from coproc MRC{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
Move to coproc from ARM reg MCR{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
Move double to ARM reg
from coproc
MRRC{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
Move double to coproc
from ARM reg
MCRR{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
Load LDC{cond} <cp_num>, <CRd>, <a_mode5>
Store STC{cond} <cp_num>, <CRd>, <a_mode5>
Table 1-7 ARM instruction set summary (continued)
Operation Assembler