The VFP Register File
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-11
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; 2nd bank
19.7.2 Operations using register banks
The register file organization supports four types of operations that the following sections
describe:
• Scalar-only instructions
• Short vector-only instructions
• Short vector instructions with scalar source on page 19-12
• Scalar instructions in short vector mode on page 19-12.
See Floating-Point Status and Control Register, FPSCR on page 20-14 for details of the LEN
and STRIDE fields and the FPSCR register.
Scalar-only instructions
An instruction is a scalar-only operation if the operands are treated as scalars and the result is a
scalar.
Clearing the LEN field in the FPSCR register selects a vector length of one iteration. For
example, if the LEN field contains b000, then the following operation writes the sum of the
single-precision values in S21 and S22 to S12:
FADDS S12, S21, S22
Some instructions can operate only on scalar data regardless of the value in the LEN field. These
instructions are:
Compare operations
FCMPS/D, FCMPZS/D, FCMPES/D, and FCMPEZS/D.
Integer conversions
FTOUIS/D, FTOUIZS/D, FTOSIS/D, FTOSIZS/D, FUITOS/D, and FSITOS/D.
Precision conversions
FCVTDS and FCVTSD.
Short vector-only instructions
Vector-only instructions require that the value in the LEN field is nonzero, and that the
destination and Fm registers are not in bank 0.
Example 19-2 shows the iterations of the following short vector instruction:
FMACS S16, S0, S8
In the example, the LEN field contains b011, selecting a vector length of four iterations, and the
STRIDE field contains b00, selecting a vector stride of one.
Example 19-2 Short vector instruction
FMACS S16, S0, S8 ; 1st iteration
FMACS S17, S1, S9 ; 2nd iteration
FMACS S18, S2, S10 ; 3rd iteration
FMACS S19, S3, S11 ; 4th and last iteration
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