The VFP Register File
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-12
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Short vector instructions with scalar source
The VFPv2 architecture enables a vector to be operated on by a scalar operand. The destination
must be a vector, that is, not in bank 0, and the Fm operand must be in bank 0.
Example 19-3 shows the iterations of the following short vector instruction with a scalar source:
FMULD D12, D8, D2
In the example, the LEN field contains b001, selecting a vector length of two iterations, and the
STRIDE field contains b00, selecting a vector stride of one.
Example 19-3 Short vector instruction with scalar source
FMULD D12, D8, D2 ; 1st iteration
FMULD D13, D9, D2 ; 2nd and last iteration
This scales the two source registers, D8 and D9, by the value in D2 and writes the new values
to D12 and D13.
Scalar instructions in short vector mode
You can mix scalar and short vector operations by carefully selecting the source and destination
registers. If the destination is in bank 0, the operation is scalar-only regardless of the value in
the LEN field. You do not have to change the LEN field from a nonzero value to b000 to perform
scalar operations.
Example 19-4 shows the sequence of operations for the following instructions:
FABSD D4, D8
FADDS S0, S0, S31
FMULS S24, S26, S1
In the example, the LEN field contains b001, selecting a vector length of two iterations, and the
STRIDE field contains b00, selecting a vector stride of one.
Example 19-4 Scalar operation in short vector mode
FABSD D4, D8 ; vector DP ABS operation on regs (D8, D9) to (D4, D5)
FABSD D5, D9
FADDS S0, S0, S31 ; scalar increment of S0 by S31
FMULS S24, S26, S1 ; vector (S26, S27) scaled by S1 and written to (S24, S25)
FMULS S25, S27, S1
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