ARM ARM1176JZF-S - Page 17

ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xvii
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List of Figures
ARM1176JZF-S Technical Reference Manual
Key to timing diagram conventions ............................................................................................ xxiv
Figure 1-1 ARM1176JZF-S processor block diagram .................................................................................. 1-8
Figure 1-2 ARM1176JZF-S pipeline stages ............................................................................................... 1-26
Figure 1-3 Typical operations in pipeline stages ........................................................................................ 1-28
Figure 1-4 Typical ALU operation ............................................................................................................... 1-28
Figure 1-5 Typical multiply operation ......................................................................................................... 1-29
Figure 1-6 Progression of an LDR/STR operation ..................................................................................... 1-30
Figure 1-7 Progression of an LDM/STM operation ..................................................................................... 1-30
Figure 1-8 Progression of an LDR that misses .......................................................................................... 1-31
Figure 2-1 Secure and Non-secure worlds ................................................................................................... 2-3
Figure 2-2 Memory in the Secure and Non-secure worlds ........................................................................... 2-6
Figure 2-3 Memory partition in the Secure and Non-secure worlds ............................................................. 2-7
Figure 2-4 Big-endian addresses of bytes within words ............................................................................. 2-15
Figure 2-5 Little-endian addresses of bytes within words .......................................................................... 2-15
Figure 2-6 Register organization in ARM state .......................................................................................... 2-20
Figure 2-7 Processor core register set showing banked registers ............................................................. 2-21
Figure 2-8 Register organization in Thumb state ....................................................................................... 2-22
Figure 2-9 ARM state and Thumb state registers relationship ................................................................... 2-23
Figure 2-10 Program status register ............................................................................................................. 2-24
Figure 2-11 LDREXB instruction .................................................................................................................. 2-30
Figure 2-12 STREXB instructions ................................................................................................................ 2-30
Figure 2-13 LDREXH instruction .................................................................................................................. 2-31
Figure 2-14 STREXH instruction .................................................................................................................. 2-32
Figure 2-15 LDREXD instruction .................................................................................................................. 2-33
Figure 2-16 STREXD instruction .................................................................................................................. 2-33
Figure 2-17 CLREX instruction ..................................................................................................................... 2-34
Figure 2-18 NOP-compatible hint instruction ............................................................................................... 2-34
Figure 3-1 System control and configuration registers ................................................................................. 3-5
Figure 3-2 MMU control and configuration registers .................................................................................... 3-7
Figure 3-3 Cache control and configuration registers .................................................................................. 3-8