Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
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B.2.13 Debug
Debug changes between ARM1136JF-S and ARM1176JZF-S processors include:
• TrustZone
• Debug test access port
• ETM
• System metrics.
TrustZone
The ARM1136JF-S processor implements the debug v6 architecture but ARM1176JZF-S
processors implement the debug v6.1 architecture. Debug v6.1 architecture accounts for
TrustZone implementations.
The ARM1176JZF-S processor supports three levels of debug:
• debug everywhere
• debug in Non-secure and Secure user
• debug in Non-secure only.
Additional input signals, SPIDEN and SPNIDEN, configure the level of debug with
corresponding bits, SUIDEN and SUNIDEN, in the CP15 Control Register where:
• SU stands for Secure User
• SP for Secure Privileged
• I for Invasive, for example watchpoints and breakpoints
• NI for Non-invasive, for example trace and performance monitoring
• DEN for Debug Enable.
EDBGRQ
In the ARM1176JZF-S processor Halting debug-mode is entered when EDBGRQ is asserted
regardless of the selection of Debug state in DSCR[15:14].
Debug test access port
The ARM1136JF-S processor requires external synchronization of the system and test clocks,
that is outside processor core.
The ARM1176JZF-S processor performs this synchronization internally.
ETM
The ETM11RV macrocell supports the ARM1136JF-S processor whereas the CoreSight
™
ETM11 macrocell supports both the ARM1136JF-S and ARM1176JZF-S processors.
System metrics
In Debug state the system metrics counters are disabled in the ARM1176JZF-S processor.
B.2.14 Level two interface
The external interfaces of the two processors are different to this extent:
• The ARM1136JF-S processor has four 64-bit AHB-Lite interfaces:
— Instruction
— Data Read
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