Glossary
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. Glossary-20
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Write completion The memory system indicates to the processor that a write has been completed at a point in the
transaction where the memory system is able to guarantee that the effect of the write is visible
to all processors in the system. This is not the case if the write is associated with a memory
synchronization primitive, or is to a Device or Strongly Ordered region. In these cases the
memory system might only indicate completion of the write when the access has affected the
state of the target, unless it is impossible to distinguish between having the effect of the write
visible and having the state of target updated.
This stricter requirement for some types of memory ensures that any side-effects of the memory
access can be guaranteed by the processor to have taken place. You can use this to prevent the
starting of a subsequent operation in the program order until the side-effects are visible.
Write-through (WT) In a write-through cache, data is written to main memory at the same time as the cache is
updated.
WT See Write-through.
Cache terminology diagram
The following diagram illustrates the following cache terminology:
• block address
• cache line
• cache set
• cache way
• index
•tag.
Tag
Tag
Tag
Tag Index Word
Hit
(way number)
Read data
(way that corresponds)
=
3
1
Tag
0
0
2
1
3
4
5
6
7
n
Byte
Cache way
Cache set
m 1
2
0
Cache line
2
Block address
Line number
Word number
Cache tag RAM Cache data RAM
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