ARM ARM1176JZF-S - Page 9

ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ix
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List of Tables
ARM1176JZF-S Technical Reference Manual
Change history ................................................................................................................................ ii
Table 1-1 TCM configurations ................................................................................................................... 1-13
Table 1-2 Double-precision VFP operations ............................................................................................. 1-20
Table 1-3 Flush-to-zero mode ................................................................................................................... 1-20
Table 1-4 Configurable options ................................................................................................................. 1-25
Table 1-5 ARM1176JZF-S processor default configurations .................................................................... 1-25
Table 1-6 Key to instruction set tables ...................................................................................................... 1-32
Table 1-7 ARM instruction set summary ................................................................................................... 1-33
Table 1-8 Addressing mode 2 ................................................................................................................... 1-40
Table 1-9 Addressing mode 2P, post-indexed only .................................................................................. 1-41
Table 1-10 Addressing mode 3 ................................................................................................................... 1-42
Table 1-11 Addressing mode 4 ................................................................................................................... 1-42
Table 1-12 Addressing mode 5 ................................................................................................................... 1-42
Table 1-13 Operand2 .................................................................................................................................. 1-43
Table 1-14 Fields ........................................................................................................................................ 1-43
Table 1-15 Condition codes ........................................................................................................................ 1-43
Table 1-16 Thumb instruction set summary ................................................................................................ 1-44
Table 2-1 Write access behavior for system control processor registers .................................................... 2-9
Table 2-2 Secure Monitor bus signals ....................................................................................................... 2-11
Table 2-3 Address types in the processor system .................................................................................
... 2-16
Table 2-4 Mode structure .......................................................................................................................... 2-17
Table 2-5 Register mode identifiers .......................................................................................................... 2-19
Table 2-6 GE[3:0] settings ........................................................................................................................ 2-26
Table 2-7 PSR mode bit values ................................................................................................................ 2-28
Table 2-8 Exception entry and exit ............................................................................................................ 2-37
Table 2-9 Exception priorities .................................................................................................................... 2-57
Table 3-1 System control coprocessor register functions ........................................................................... 3-3
Table 3-2 Summary of CP15 registers and operations ............................................................................. 3-14
Table 3-3 Summary of CP15 MCRR operations ....................................................................................... 3-19
Table 3-4 Main ID Register bit functions ................................................................................................... 3-20