ARM ARM1176JZF-S - Page 14

List of Tables
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Table 8-64 Cacheable Write-Through or Noncacheable STM11 ................................................................ 8-33
Table 8-65 Cacheable Write-Through or Noncacheable STM12 ................................................................ 8-34
Table 8-66 Cacheable Write-Through or Noncacheable STM13 ................................................................ 8-34
Table 8-67 Cacheable Write-Through or Noncacheable STM14 ................................................................ 8-35
Table 8-68 Cacheable Write-Through or Noncacheable STM15 ................................................................ 8-35
Table 8-69 Cacheable Write-Through or Noncacheable STM16 ................................................................ 8-36
Table 8-70 Example Peripheral Interface reads and writes ........................................................................ 8-37
Table 9-1 Reset modes ............................................................................................................................. 9-10
Table 11-1 Coprocessor instructions .......................................................................................................... 11-3
Table 11-2 Coprocessor control signals ...................................................................................................... 11-4
Table 11-3 Pipeline stage update ............................................................................................................... 11-7
Table 11-4 Addressing of queue buffers ................................................................................................... 11-10
Table 11-5 Retirement conditions ............................................................................................................. 11-20
Table 12-1 VIC port signals ......................................................................................................................... 12-3
Table 13-1 Terms used in register descriptions .......................................................................................... 13-5
Table 13-2 CP14 debug register map ......................................................................................................... 13-5
Table 13-3 Debug ID Register bit field definition ......................................................................................... 13-7
Table 13-4 Debug Status and Control Register bit field definitions ............................................................. 13-8
Table 13-5 Data Transfer Register bit field definitions .............................................................................. 13-12
Table 13-6 Vector Catch Register bit field definitions ............................................................................... 13-14
Table 13-7 Summary of debug entry and exception conditions ................................................................ 13-14
Table 13-8 Processor breakpoint and watchpoint registers ...................................................................... 13-16
Table 13-9 Breakpoint Value Registers, bit field definition ........................................................................ 13-17
Table 13-10 Processor Breakpoint Control Registers ................................................................................. 13-17
Table 13-11 Breakpoint Control Registers, bit field definitions ................................................................... 13-18
Table 13-12 Meaning of BCR[22:20] bits .................................................................................................... 13-19
Table 13-13 Processor Watchpoint Value Registers .................................................................................. 13-20
Table 13-14 Watchpoint Value Registers, bit field definitions ..................................................................... 13-21
Table 13-15 Processor Watchpoint Control Registers ................................................................................ 13-21
Table 13-16 Watchpoint Control Registers, bit field definitions ................................................................... 13-21
Table 13-17 Debug State Cache Control Register bit functions ................................................................. 13-23
Table 13-18 Debug State MMU Control Register bit functions ................................................................... 13-24
Table 13-19 CP14 debug instructions ......................................................................................................... 13-26
Table 13-20 Debug instruction execution .................................................................................................... 13-27
Table 13-21 Secure debug behavior ........................................................................................................... 13-28
Table 13-22 Behavior of the processor on debug events ........................................................................... 13-33
Table 13-23 Setting of CP15 registers on debug events ............................................................................ 13-34
Table 13-24 Values in the link register after exceptions ............................................................................. 13-36
Table 13-25 Read PC value after Debug state entry .................................................................................. 13-39
Table 13-26 Example memory operation sequence ................................................................................... 13-41
Table 14-1 Supported public instructions .................................................................................................... 14-6
Table 14-2 Scan chain 7 register map ...................................................................................................... 14-19
Table 15-1 Instruction interface signals ...................................................................................................... 15-2
Table 15-2 ETMIACTL[17:0] ....................................................................................................................... 15-3
Table 15-3 ETMIASECCTL[1:0] .................................................................................................................. 15-4
Table 15-4 Data address interface signals .................................................................................................. 15-4
Table 15-5 ETMDACTL[17:0] ...................................................................................................................... 15-5
Table 15-6 Data value interface signals ...................................................................................................... 15-6
Table 15-7 ETMDDCTL[3:0] ....................................................................................................................... 15-6
Table 15-8 ETMPADV[2:0] .......................................................................................................................... 15-6
Table 15-9 Coprocessor interface signals ................................................................................................... 15-7
Table 15-10 ETMCPSECCTL[1:0] format ..................................................................................................... 15-7
Table 15-11 Other connections ..................................................................................................................... 15-8
Table 16-1 Pipeline stages .......................................................................................................................... 16-3
Table 16-2 Definition of cycle timing terms ................................................................................................. 16-5
Table 16-3 Register interlock examples ...................................................................................................... 16-6
Table 16-4 Data Processing Instruction cycle timing behavior if destination is not PC ............................... 16-7
Table 16-5 Data Processing Instruction cycle timing behavior if destination is the PC ............................... 16-7
Table 16-6 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... 16-9
Table 16-7 ARMv6 media data-processing instructions cycle timing behavior ......................................... 16-10