ARM ARM1176JZF-S - Page 15

List of Tables
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Table 16-8 ARMv6 sum of absolute differences instruction timing behavior ............................................ 16-11
Table 16-9 Example interlocks .................................................................................................................. 16-11
Table 16-10 Example multiply instruction cycle timing behavior ................................................................. 16-12
Table 16-11 Branch instruction cycle timing behavior ................................................................................. 16-14
Table 16-12 Processor state updating instructions cycle timing behavior .................................................. 16-15
Table 16-13 Cycle timing behavior for stores and loads, other than loads to the PC ................................. 16-16
Table 16-14 Cycle timing behavior for loads to the PC ............................................................................... 16-17
Table 16-15 <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation ............... 16-17
Table 16-16 Load and Store Double instructions cycle timing behavior ..................................................... 16-19
Table 16-17 <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation ............. 16-19
Table 16-18 Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC .......
16-21
Table 16-19 Cycle timing behavior of Load Multiples, where the PC is in the register list .......................... 16-22
Table 16-20 RFE and SRS instructions cycle timing behavior .................................................................... 16-23
Table 16-21 Synchronization Instructions cycle timing behavior ................................................................ 16-24
Table 16-22 Coprocessor Instructions cycle timing behavior ...................................................................... 16-25
Table 16-23 SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior ......................... 16-26
Table 17-1 Global signals ........................................................................................................................... 17-3
Table 17-2 AXI signals ................................................................................................................................ 17-3
Table 17-3 Coprocessor signals ................................................................................................................. 17-5
Table 17-4 ETM interface signals ............................................................................................................... 17-5
Table 17-5 Interrupt signals ........................................................................................................................ 17-5
Table 17-6 Debug interface signals ............................................................................................................ 17-6
Table 17-7 Test signals ............................................................................................................................... 17-6
Table 17-8 Static configuration signals ....................................................................................................... 17-6
Table 17-9 TrustZone internal signals ......................................................................................................... 17-7
Table 19-1 VFP11 MCR instructions ........................................................................................................... 19-6
Table 19-2 VFP11 MRC instructions ........................................................................................................... 19-6
Table 19-3 VFP11 MCRR instructions ........................................................................................................ 19-6
Table 19-4 VFP11 MRRC instructions ........................................................................................................ 19-7
Table 19-5 Single-precision data memory images and byte addresses ..................................................... 19-9
Table 19-6 Double-precision data memory images and byte addresses .................................................... 19-9
Table 19-7 Single-precision three-operand register usage ....................................................................... 19-13
Table 19-8 Single-precision two-operand register usage .......................................................................... 19-13
Table 19-9 Double-precision three-operand register usage ...................................................................... 19-13
Table 19-10 Double-precision two-operand register usage ........................................................................ 19-13
Table 20-1 Default NaN values ................................................................................................................... 20-4
Table 20-2 QNaN and SNaN handling ........................................................................................................ 20-5
Table 20-3 VFP11 system registers .......................................................................................................... 20-12
Table 20-4 Accessing VFP11 system registers ........................................................................................ 20-13
Table 20-5 FPSID bit fields ....................................................................................................................... 20-14
Table 20-6 Encoding of the Floating-Point Status and Control Register ................................................... 20-15
Table 20-7 Vector length and stride combinations .................................................................................... 20-16
Table 20-8 Encoding of the Floating-Point Exception Register ................................................................. 20-17
Table 20-9 Media and VFP Feature Register 0 bit functions .................................................................... 20-19
Table 20-10 Media and VFP Feature Register 1 bit functions .................................................................... 20-20
Table 21-1 Single-precision source register locking ................................................................................... 21-8
Table 21-2 Single-precision source register clearing .................................................................................. 21-9
Table 21-3 Double-precision source register locking ................................................................................ 21-10
Table 21-4 Double-precision source register clearing for one-cycle instructions ...................................... 21-11
Table 21-5 Double-precision source register clearing for two-cycle instructions ...................................... 21-11
Table 21-6 FCMPS-FMSTAT RAW hazard .............................................................................................. 21-13
Table 21-7 FLDM-FADDS RAW hazard ................................................................................................... 21-14
Table 21-8 FLDM-short vector FADDS RAW hazard ................................................................................ 21-14
Table 21-9 FMULS-FADDS RAW hazard ................................................................................................. 21-15
Table 21-10 Short vector FMULS-FLDMS WAR hazard ............................................................................. 21-15
Table 21-11 Short vector FMULS-FLDMS WAR hazard in RunFast mode ................................................ 21-16
Table 21-12 FLDM-FLDS-FADDS resource hazard ................................................................................... 21-18
Table 21-13 FLDM-short vector FMULS resource hazard .......................................................................... 21-18
Table 21-14 Short vector FDIVS-FADDS resource hazard ......................................................................... 21-19