ARM ARM1176JZF-S - Page 5

Contents
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. v
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2.12 Exceptions ............................................................................................................. 2-36
2.13 Software considerations ........................................................................................ 2-59
Chapter 3 System Control Coprocessor
3.1 About the system control coprocessor ..................................................................... 3-2
3.2 System control processor registers ....................................................................... 3-13
Chapter 4 Unaligned and Mixed-endian Data Access Support
4.1 About unaligned and mixed-endian support ............................................................ 4-2
4.2 Unaligned access support ....................................................................................... 4-3
4.3 Endian support ......................................................................................................... 4-6
4.4 Operation of unaligned accesses .......................................................................... 4-13
4.5 Mixed-endian access support ................................................................................ 4-17
4.6 Instructions to reverse bytes in a general-purpose register ................................... 4-20
4.7 Instructions to change the CPSR E bit .................................................................. 4-21
Chapter 5 Program Flow Prediction
5.1 About program flow prediction ................................................................................. 5-2
5.2 Branch prediction ..................................................................................................... 5-4
5.3 Return stack ............................................................................................................. 5-7
5.4 Memory Barriers ...................................................................................................... 5-8
5.5 ARM1176JZF-S IMB implementation .................................................................... 5-10
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................................ 6-2
6.2 TLB organization ...................................................................................................... 6-4
6.3 Memory access sequence ....................................................................................... 6-7
6.4 Enabling and disabling the MMU ............................................................................. 6-9
6.5 Memory access control .......................................................................................... 6-11
6.6 Memory region attributes ....................................................................................... 6-14
6.7 Memory attributes and types ................................................................................. 6-20
6.8 MMU aborts ........................................................................................................... 6-27
6.9 MMU fault checking ............................................................................................... 6-29
6.10 Fault status and address ....................................................................................... 6-34
6.11 Hardware page table translation ............................................................................ 6-36
6.12 MMU descriptors .................................................................................................... 6-43
6.13 MMU software-accessible registers ....................................................................... 6-53
Chapter 7 Level One Memory System
7.1 About the level one memory system ........................................................................ 7-2
7.2 Cache organization .................................................................................................. 7-3
7.3 Tightly-coupled memory .......................................................................................... 7-7
7.4 DMA ....................................................................................................................... 7-10
7.5 TCM and cache interactions .................................................................................. 7-12
7.6 Write buffer ............................................................................................................ 7-16
Chapter 8 Level Two Interface
8.1 About the level two interface .................................................................................... 8-2
8.2 Synchronization primitives ....................................................................................... 8-6
8.3 AXI control signals in the processor ........................................................................ 8-8
8.4 Instruction Fetch Interface transfers ...................................................................... 8-14
8.5 Data Read/Write Interface transfers ...................................................................... 8-15
8.6 Peripheral Interface transfers ................................................................................ 8-37
8.7 Endianness ............................................................................................................ 8-38
8.8 Locked access ....................................................................................................... 8-39
Chapter 9 Clocking and Resets
9.1 About clocking and resets ........................................................................................ 9-2