Contents
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. vi
ID012310 Non-Confidential, Unrestricted Access
9.2 Clocking and resets with no IEM ............................................................................. 9-3
9.3 Clocking and resets with IEM .................................................................................. 9-5
9.4 Reset modes .......................................................................................................... 9-10
Chapter 10 Power Control
10.1 About power control ............................................................................................... 10-2
10.2 Power management ............................................................................................... 10-3
10.3 VFP shutdown ....................................................................................................... 10-6
10.4 Intelligent Energy Management ............................................................................. 10-7
Chapter 11 Coprocessor Interface
11.1 About the coprocessor interface ............................................................................ 11-2
11.2 Coprocessor pipeline ............................................................................................. 11-3
11.3 Token queue management .................................................................................... 11-9
11.4 Token queues ...................................................................................................... 11-12
11.5 Data transfer ........................................................................................................ 11-15
11.6 Operations ........................................................................................................... 11-19
11.7 Multiple coprocessors .......................................................................................... 11-22
Chapter 12 Vectored Interrupt Controller Port
12.1 About the PL192 Vectored Interrupt Controller ...................................................... 12-2
12.2 About the processor VIC port ................................................................................ 12-3
12.3 Timing of the VIC port ............................................................................................ 12-5
12.4 Interrupt entry flowchart ......................................................................................... 12-7
Chapter 13 Debug
13.1 Debug systems ...................................................................................................... 13-2
13.2 About the debug unit .............................................................................................. 13-3
13.3 Debug registers ..................................................................................................... 13-5
13.4 CP14 registers reset ............................................................................................ 13-25
13.5 CP14 debug instructions ...................................................................................... 13-26
13.6 External debug interface ...................................................................................... 13-28
13.7 Changing the debug enable signals .................................................................... 13-31
13.8 Debug events ....................................................................................................... 13-32
13.9 Debug exception .................................................................................................. 13-35
13.10 Debug state ......................................................................................................... 13-37
13.11 Debug communications channel .......................................................................... 13-42
13.12 Debugging in a cached system ............................................................................ 13-43
13.13 Debugging in a system with TLBs ....................................................................... 13-44
13.14 Monitor debug-mode debugging .......................................................................... 13-45
13.15 Halting debug-mode debugging ........................................................................... 13-50
13.16 External signals ................................................................................................... 13-52
Chapter 14 Debug Test Access Port
14.1 Debug Test Access Port and Debug state ............................................................. 14-2
14.2 Synchronizing RealView ICE ................................................................................. 14-3
14.3 Entering Debug state ............................................................................................. 14-4
14.4 Exiting Debug state ................................................................................................ 14-5
14.5 The DBGTAP port and debug registers ................................................................. 14-6
14.6 Debug registers ..................................................................................................... 14-8
14.7 Using the Debug Test Access Port ...................................................................... 14-21
14.8 Debug sequences ................................................................................................ 14-29
14.9 Programming debug events ................................................................................. 14-40
14.10 Monitor debug-mode debugging .......................................................................... 14-42
Chapter 15 Trace Interface Port
15.1 About the ETM interface ........................................................................................ 15-2
To Next Page
Loading...
