Contents
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. vii
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Chapter 16 Cycle Timings and Interlock Behavior
16.1 About cycle timings and interlock behavior ............................................................ 16-2
16.2 Register interlock examples ................................................................................... 16-6
16.3 Data processing instructions .................................................................................. 16-7
16.4 QADD, QDADD, QSUB, and QDSUB instructions ................................................ 16-9
16.5 ARMv6 media data-processing ............................................................................ 16-10
16.6 ARMv6 Sum of Absolute Differences (SAD) ........................................................ 16-11
16.7 Multiplies .............................................................................................................. 16-12
16.8 Branches .............................................................................................................. 16-14
16.9 Processor state updating instructions .................................................................. 16-15
16.10 Single load and store instructions ........................................................................ 16-16
16.11 Load and Store Double instructions ..................................................................... 16-19
16.12 Load and Store Multiple Instructions ................................................................... 16-21
16.13 RFE and SRS instructions ................................................................................... 16-23
16.14 Synchronization instructions ................................................................................ 16-24
16.15 Coprocessor instructions ..................................................................................... 16-25
16.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions ...................... 16-26
16.17 No operation ........................................................................................................ 16-27
16.18 Thumb instructions .............................................................................................. 16-28
Chapter 17 AC Characteristics
17.1 Processor timing diagrams .................................................................................... 17-2
17.2 Processor timing parameters ................................................................................. 17-3
Chapter 18 Introduction to the VFP coprocessor
18.1 About the VFP11 coprocessor ............................................................................... 18-2
18.2 Applications ........................................................................................................... 18-3
18.3 Coprocessor interface ............................................................................................ 18-4
18.4 VFP11 coprocessor pipelines ................................................................................ 18-5
18.5 Modes of operation .............................................................................................. 18-11
18.6 Short vector instructions ...................................................................................... 18-13
18.7 Parallel execution of instructions ......................................................................... 18-14
18.8 VFP11 treatment of branch instructions .............................................................. 18-15
18.9 Writing optimal VFP11 code ................................................................................ 18-16
18.10 VFP11 revision information .................................................................................. 18-17
Chapter 19 The VFP Register File
19.1 About the register file ............................................................................................. 19-2
19.2 Register file internal formats .................................................................................. 19-3
19.3 Decoding the register file ....................................................................................... 19-5
19.4 Loading operands from ARM11 registers .............................................................. 19-6
19.5 Maintaining consistency in register precision ........................................................ 19-8
19.6 Data transfer between memory and VFP11 registers ............................................ 19-9
19.7 Access to register banks in CDP operations ....................................................... 19-10
Chapter 20 VFP Programmer’s Model
20.1 About the programmer’s model ............................................................................. 20-2
20.2 Compliance with the IEEE 754 standard ............................................................... 20-3
20.3 ARMv5TE coprocessor extensions ........................................................................ 20-8
20.4 VFP11 system registers ....................................................................................... 20-12
Chapter 21 VFP Instruction Execution
21.1 About instruction execution .................................................................................... 21-2
21.2 Serializing instructions ........................................................................................... 21-3
21.3 Interrupting the VFP11 coprocessor ...................................................................... 21-4
21.4 Forwarding ............................................................................................................. 21-5
21.5 Hazards ................................................................................................................. 21-6
21.6 Operation of the scoreboards ................................................................................ 21-7
21.7 Data hazards in full-compliance mode ................................................................. 21-13
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