Maxim Integrated MAX32665 - Table 4-70: Error Correction Coding Interrupt Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 109 of 457
Error Correction Coding Not Double Error Detected
GCR_ECC_NDED
[0x0068]
Bits
Field
Access
Reset
Description
1
sysram1eccnded
R/W1C
1
System RAM1 Not Double ECC Error Detected
When cleared, indicates that there is a single correctable error in the RAM1
block. Write to 1 to clear the flag.
0: Error
1: No Error
0
sysram0eccnded
R/W1C
1
System RAM0 Not Double ECC Error Detected
When cleared, indicates that there is a single correctable error in the RAM0
block. Write to 1 to clear the flag.
0: Error
1: No Error
Table 4-70: Error Correction Coding Interrupt Enable Register
Error Correction Coding Interrupt Enable
GCR_ECC_IRQEN
[0x006C]
Bits
Field
Access
Reset
Description
31:13
-
RO
0
Reserved.
12
fl1eccen
R/W
0
Flash1 ECC Error Interrupt Enable
0: Disabled
1: Enabled
11
fl0eccen
R/W
0
Flash0 ECC Error Interrupt Enable
0: Disabled
1: Enabled
10
Iicxpeccen
R/W
0
SPIXF Instruction Cache ECC Error Interrupt Enable
0: Disabled
1: Enabled
9
ec1eccen
R/W
0
Instruction Cache 1 ECC Error Interrupt Enable
0: Disabled
1: Enabled
8
ec0eccen
R/W
0
Instruction Cache 0 ECC Error Interrupt Enable
0: Disabled
1: Enabled
7:6
-
RO
0
Reserved.
5
eccsysram5en
R/W
0
Sysram5 ECC Error Interrupt Enable
0: Disabled
1: Enabled
4
eccsysram4en
R/W
0
Sysram4 ECC Error Interrupt Enable
0: Disabled
1: Enabled
3
eccsysram3en
R/W
0
Sysram3 ECC Error Interrupt Enable
0: Disabled
1: Enabled
2
eccsysram2en
R/W
0
Sysram2 ECC Error Interrupt Enable
0: Disabled
1: Enabled
1
eccsysram1en
R/W
0
Sysram1 ECC Error Interrupt Enable
0: Disabled
1: Enabled
0
eccsysram0en
R/W
0
Sysram0 ECC Error Interrupt Enable
0: Disabled
1: Enabled