MAX32665-MAX32668 User Guide
Maxim Integrated Page 168 of 457
Figure 8-6. Simplified SPIXR Block Diagram
I D
ARM
®
Cortex
®
-M4
CPU1
AHB AHB SYSTEM B US
EXTERNAL
SPI-XIP FLA SH
ARM
®
Cortex
®
-M4
CPU0
I D
GCR_SCON
dcache _dis
SPIXR CACHE
BYPAS S
SPIXR
INTERFACE
SPIXR CACHE
CONTROLLER (SRCC)
LINE BUFFER
16KB EXTERNAL
SPI RAM MEMORY
CACHE
8.3.1 SPIXR Master Controller Registers
See Table 3-1: APB Peripheral Base Address Map for the SPIXR Peripheral Base Address
Table 8-24. SPIXR Master Controller Register Offsets, Names, Access and Descriptions
SPIXR Master Signals Control Register
SPIXR Transmit Packet Size Register
SPIXR Static Configuration Register
SPIXR Slave Select Timing Register
SPIXR Master Baud Rate Register
SPIXR DMA Control Register
SPIXR Interrupt Status Flags Register
SPIXR Interrupt Enable Register
SPIXR Wakeup Status Flags Register
SPIXR Wakeup Enable Register