MAX32665-MAX32668 User Guide
Maxim Integrated Page 226 of 457
Data Movement From Source to DMA
Table 9-3 shows the fields that control the burst movement of data into the DMA FIFO. The source is a peripheral or
memory.
Table 9-3: Data Movement from Source to DMA FIFO
If the increment enable is set, this increments on every read cycle of the
burst. This field is ignored when the DMA source is a peripheral.
Number of bytes to transfer
before a CTZ condition occurs
This register is decremented on each read of the burst.
This maximum number of bytes moved during the burst read.
This determines the maximum data width used during each read of the
AHB burst (byte, two bytes, or four bytes). The actual AHB width might
be less if DMACHn_CNT is not great enough to supply all the needed
bytes.
Increments DMACHn_SRC. This field is ignored when the DMA source is a
peripheral.
9.2.3 Data Movement From the DMA to Destination
Table 9-4 shows the fields that control the burst movement of data out of the DMA FIFO. The destination is a peripheral or
memory.
Table 9-4: Data Movement from the DMA FIFO to Destination
If the increment enable is set, this increments on every write cycle of the
burst. This field is ignored when the DMA destination is a peripheral.
The maximum number of bytes moved during a single AHB read/write
burst.
This determines the maximum data width used during each write of the
AHB burst (one byte, two bytes, or four bytes).
Destination increment enable
Increments DMACHn_DST. This field is ignored when the DMA
destination is a peripheral.