MAX32665-MAX32668 User Guide
Maxim Integrated Page 334 of 457
16.6 Counter Mode (010b)
In Counter mode, the timer peripheral increments TMRn_CNT when a transition occurs on the timer pin. When
TMRn_CNT = TMRn_CMP, the interrupt bit is set and the TMRn_CNT register is set to 0x0000 0001 and continues
incrementing. The timer can be configured to increment on either the rising edge or the falling edge, but not both.
The timer prescaler setting has no effect in this mode. The frequency of the timer’s input signal (f
CTR_CLK
) must not exceed 25
percent of the PCLK frequency as shown in the following equation:
Equation 16-4: Counter Mode Maximum Clock Frequency
Figure 16-3: Counter Mode Diagram
TMR_CN.ten
TMR_CNT
0x0000 0000*
0x0000 0001*
TMR_INT.irq
TMR_CN.cmp
* TMR_CNT IS RELOADED WITH 0x0000 0001 AT THE END OF EA CH TIMER PERIOD. FIRMWARE SETS THE INITIAL VALUE IN TMR_CNT
PRIOR TO ENABLING THE TIM ER.
FIRMWARE CLEARS
TMR_CN.tpol = 1
TMR_CN.tpol = 0
TMR PIN
(INPUT)
0x0000 0002
PCLK
(INTERNAL)
MINIMUM INPUT PULSE
4×PCLK
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