3.6 Error Correction Coding (ECC) Module
This device features an Error Correction Coding (ECC) module which helps ensures data integrity by detecting and correcting
bit corruption of memory arrays. More specific, this feature is Single Error Correcting, Double Error Detecting (SEC-DED). It
corrects any single bit flip, detects 2-bit errors, and features a transparent zero wait state operation for reads.
The ECC works by creating check bits for all data written to memory. These check bits are then stored along with the data.
During a read, both the data and check bits are used to determine if one or more bits have become corrupt. If a single bit
has been corrupted this can be corrected. If two bits have been corrupted, it will be detected, but not corrected.
If only one bit is determined to be corrupt, reads will contain the “corrected” value. Reading memory does not correct the
errored value stored at the read memory location. It is up to the application firmware to determine the appropriate time
and method to write the correct data to memory. It is strongly recommended that the application firmware correct the
memory as soon as possible to minimize the chance of a second bit from becoming corrupt, resulting in data loss. Since ECC
error checking only occurs during a “read” operation, it is recommended that the application periodically “reads” critical
memory so that errors can be identified and corrected.
3.6.1 SRAM
To integrate the ECC SEC-DED module into a RAM, there must be a secondary RAM instance to store the check bits. In the
case of a 32-bit wide RAM, 7 check bits are needed. The secondary check bit RAM can hold the 7 check bits in each byte,
therefore needs ¼ the number of words as the RAM itself. Also, the address sent to the check bit RAM is divided by 4 to
map the 32-bit data words to 8-bit check bit addresses.
For example, a 32-bit by 8192 word RAM would need a 32-bit by 2048 word sized secondary RAM instance. When ECC is
enabled, each system RAM module requires an appropriately sized secondary RAM.
3.6.2 FLASH
The flash lines will need to be larger in width to so that the check bits can be placed on the same line as the data. 128 data
bits would require 9 check bits for a total of 137 bits. This will require changes to the flash controller to write these check
bits each time any of the 128 data bits on a line are changed. Also, any write that is less than the full width of the data will
require a read first to fetch the other unchanging bytes to properly calculate the check bits. This will cause an extra delay.
3.6.3 Cache
Any type of ECC error (single or double) is treated as a cache miss. There are separate ECC check bits for both the data RAM
and tag RAM inside the cache.
3.6.4 Limitations
Any read from non-initialized memory could trigger an ECC error since the random check bits will most likely not match the
random data bits. Writing the memory to all zeroes at bootup can prevent this at the expense of the time required.
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