Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 37 of 457
3.2 Standard Memory Regions
Several standard memory regions are defined for the Arm Cortex-M4 architecture; the use of many of these is optional for
the system integrator. At a minimum, the MAX32665—MAX32668, Cortex-M4-based devices, must contain some code and
data memory for application code and variable/stack use, as well as certain components which are part of the instantiated
core.
3.2.1 Code Space
The code space area of memory is designed to contain the primary memory used for code execution by the device. This
memory area is defined from byte address range 0x0000 0000 to 0x1FFF FFFF (0.5GB maximum). Two different standard
core bus masters are used by the Cortex-M4 core and Arm debugger to access this memory area. The I-Code AHB bus
master is used for instruction decode fetching from code memory, while the D-Code AHB bus master is used for data
fetches from code memory. This is arranged so that data fetches avoid interfering with instruction execution.
The MAX32665—MAX32668 code memory mapping is illustrated in Figure 3-1: Code Memory Mapping. The code space
memory area contains the main internal flash memory, which holds most of the instruction code that will be executed on
the device. The internal flash memory is mapped into both code and data space from 0x1000 0000 to 0x100F FFFF. It is
partitioned as two 512KB blocks of usable flash plus extra flash storage for Error Correction Coding (ECC) check bits, if ECC is
enabled. This additional storage is not user accessible, even when ECC is disabled.
This program memory area must also contain the default system vector table and the initial settings for all system
exception handlers and interrupt handlers. The reset vector for the device is 0x0000 0000 where a vector to re-direct to
0x1000 0000 is located.
The code space memory on the MAX32665—MAX32668 also contains the mapping for the flash information block, from
0x1080 0000 to 0x1080 7FFF. However, this mapping is generally only present during Maxim Integrated production test; it is
disabled once the information block has been loaded with valid data and the info block lockout option has been set. This
memory is accessible for data reads only and cannot be used for code execution.
Optionally, the SPIXF (SPI Execute In Place Flash) and the SPIXR (SPI Execute In Place RAM) modules can be used to expand
the available code and data memory space. This expansion consists of mapping the contents of an external SPI flash
memory device (up to 128MB) or an external SPI RAM memory device (up to 512MB) into a read-only area of the code
memory map. If enabled, the external SPIXF memory is mapped starting at byte address 0x0800 0000 up to a maximum of
0x0FFF FFFF (for a 128MB device). Also, if enabled, the external SPIXR memory is mapped starting at byte 0x8000 000 up to
a maximum of 0x9FFF FFFF (for a 512MB device). This external memory can be used for code execution as well as static
data storage.
3.2.2 SRAM Space
The SRAM area of memory is intended to contain the primary SRAM data memory of the device and is defined from byte
address range 0x2000 0000 to 0x3FFF FFFF (0.5GB maximum). This memory can be used for general purpose variable and
data storage, code execution, and the Arm Cortex-M4 stack.
The MAX32665—MAX32668 data memory mapping is illustrated in Figure 3-2: Data Memory Mapping. This memory area
contains the main system SRAM. The size of the internal SRAM is 560KB when not using ECC. Its address range is 0x2000
0000 to 0x2008 BFFF. If ECC is enabled, the SRAM size decreases to 448KB. The address range with ECC enabled is
0x2000 0000 to 0x2006 FFFF.
The entirety of the SRAM memory space on the MAX32665—MAX32668 is contained within the dedicated Arm Cortex-M4
SRAM bit-banding region from 0x2000 0000 to 0x200F FFFF (1MB maximum for bit-banding). This means that the CPU can
access the entire SRAM either using standard byte/word/doubleword access or using bit-banding operations. The bit-
banding mechanism allows any single bit of any given SRAM byte address location to be set, cleared, or read individually by
reading from or writing to a corresponding doubleword (32-bit wide) location in the bit-banding alias area.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English