Maxim Integrated MAX32665 - Table 4-55: Reset Register 0

MAX32665-MAX32668 User Guide
Maxim Integrated Page 87 of 457
System Control
GCR_SCON
[0x0000]
Bits
Field
Access
Reset
Description
9
dcache_dis
R/W
0
SPIXR Cache Controller (SRCC) Disable
This disables the SRCC used for SPIXR code and data cache. Setting this field
disables the cache and bypasses the cache line buffer.
0: Cache enabled
1: Cache disabled and line buffer bypassed
8
-
RO
0
Reserved
Do not modify this field.
7
dcache_flush
R/W
0
SPIXR Cache (SRCC) Flush
Write 1 to flush the SPIXR 16KB cache. This bit is automatically cleared to 0
when the flush is complete. Writing 0 has no effect.
0: Memory flush not in progress.
1: Memory flush in progress.
6
ccache_flush
R/W
0
ICC0/ICC1/SFCC Code Cache Flush
Write 1 to flush all three caches. This bit is automatically cleared to 0 when the
flush is complete. Writing 0 has no effect.
0: Memory flush not in progress.
1: Memory flush in progress.
5
-
RO
0
Reserved
Do not modify this field.
4
flash_page_flip
R/*
0
Flash Page Flip Flag
Flips the bottom and top halves of Flash memory. This bit is controlled by
hardware. Firmware should not change the state of this bit during normal
operation. Any change to this bit also flushes both code and data caches.
0: Physical layout matches logical layout
1: Top and Bottom halves flipped
3
-
RO
0
Reserved
Do not modify this field.
2:1
sbusarb
R/W
1
System Bus Arbitration Scheme
00: Fixed Burst
01: Round-Robin
10: Reserved
11: Reserved
0
-
R/W
0
Boundary Scan Tap Enable
Reserved
Do not modify this field.
Table 4-55: Reset Register 0
Reset 0
GCR_RST0
[0x0004]
Bits
Field
Access
Reset
Description
31
sys_rst
R/W
0
System Reset
Write 1 to reset.
0: Not in reset
1: Reset in progress.