MAX32665-MAX32668 User Guide
Maxim Integrated Page 372 of 457
18.4.2 Sub-Second Alarm
The RTC_SSECA and RTC_CTRL.ssec_alarm_en field control the sub-second alarm. Writing RTC_SSECA sets the starting value
for the sub-second alarm counter. Writing the Sub-Second Alarm Enable (RTC_CTRL.ssec_alarm_en) bit to 1 enables the
sub-second alarm. Once enabled, an internal alarm counter begins incrementing from the RTC_SSECA value. When the
counter rolls over from 0xFFFF FFFF to 0x0000 0000, hardware sets the RTC_CTRL.ssec_alarm_fl bit triggering the alarm. At
the same time, hardware also reloads the counter with the value previously written to RTC_SSECA.rssa.
You must disable the sub-second interval alarm, RTC_CTRL.ssec_alarm_en, prior to changing the interval alarm value,
RTC_SSECA.
The delay (uncertainty) associated with enabling the sub-second alarm is up to one period of the sub-second clock. This
uncertainty is propagated to the first interval alarm. Thereafter, if the interval alarm remains enabled, the alarm triggers
after each sub-second interval as defined without the first alarm uncertainty because the sub-second alarm is an auto-
reload timer. Enabling the sub-second alarm with the sub-second alarm register set to 0 (RTC_SSECA = 0) results in the
maximum sub-second alarm interval.
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