Maxim Integrated MAX32665 - AES Key Registers; AES Key Register Details; Table 4-78: AES Key Register Summary; Table 4-79: AES Key 0 and 1 Registers

MAX32665-MAX32668 User Guide
Maxim Integrated Page 114 of 457
Function Control 0
GCR_FCR
[0x0000]
Bits
Field
Access
Reset
Description
17
qspi0_fnc_sel
R/W
0
QSPI0 Function Select
0: High speed 96MHz oscillator
1: External clock input
Note: See the GPIO chapter for the external clock input pin
16
usb_clk_sel
R/W
0
USB Reference Clock Source Select
This selects the clock source for the USB Hi-Speed Interface.
0: High speed 96MHz oscillator
1: External clock input
See the GPIO chapter for the external clock input pin
15:0
-
RO
0
Reserved
Do not modify this field.
4.20 AES Key Registers
See Table 3-1: APB Peripheral Base Address Map for the AES Key Registers’ Peripheral Base Address.
Table 4-78: AES Key Register Summary
Offset
Register
Name
[0x0000]
AES_KEY0
128-bit AES Key Register 0
[0x0080]
AES_KEY1
128-bit AES Key Register 1
[0x0100]
AES_KEY2
128-bit AES Key Register 2
[0x0180]
AES_KEY3
128-bit AES Key Register 3
4.21 AES Key Register Details
Table 4-79: AES Key 0 and 1 Registers
AES Key 0
AES_KEY0
[0x0000]
AES Key 1
AES_KEY1
[0x0080]
Bits
Field
Access
Reset
Description
127:0
aes_key
R/W
0
AES 128-bit Key Registers
These two registers make up the 256-bit AES key, with the most significant
bits in AES_KEY1 and the least significant bits in AES_KEY0.
This register is reset only on AoD Reset.
Table 4-80: AES Key 2 and 3 Registers
AES Key 2
AES_KEY2
[0x0100]
AES Key 3
AES_KEY3
[0x0180]
Bits
Field
Access
Reset
Description
127:0
aes_key
R/W
-
AES 128-bit Key Registers
Each of these registers are loaded at system initialization with user-
defined 128-bit keys.
See the secure bootloader section in the TPU supplement for
more information.